124 lines
7.0 KiB
C
124 lines
7.0 KiB
C
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/* ###################################################################
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** This component module is generated by Processor Expert. Do not modify it.
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** Filename : dmaController1.h
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** Project : S32K118_reva1_BaseDemo_LQFP48
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** Processor : S32K118_48
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** Component : edma
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** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000
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** Repository : SDK_S32K1xx_15
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** Compiler : GNU C Compiler
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** Date/Time : 2021-09-16, 21:35, # CodeGen: 5
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** Contents :
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** EDMA_DRV_Init - status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t...
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** EDMA_DRV_Deinit - status_t EDMA_DRV_Deinit(void);
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** EDMA_DRV_ChannelInit - status_t EDMA_DRV_ChannelInit(edma_chn_state_t * edmaChannelState,const...
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** EDMA_DRV_ReleaseChannel - status_t EDMA_DRV_ReleaseChannel(uint8_t channel);
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** EDMA_DRV_StartChannel - status_t EDMA_DRV_StartChannel(uint8_t channel);
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** EDMA_DRV_StopChannel - status_t EDMA_DRV_StopChannel(uint8_t channel);
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** EDMA_DRV_InstallCallback - status_t EDMA_DRV_InstallCallback(uint8_t channel,edma_callback_t...
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** EDMA_DRV_GetChannelStatus - edma_chn_status_t EDMA_DRV_GetChannelStatus(uint8_t channel);
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** EDMA_DRV_PushConfigToReg - void EDMA_DRV_PushConfigToReg(uint8_t channel,edma_transfer_config_t * config);
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** EDMA_DRV_PushConfigToSTCD - void EDMA_DRV_PushConfigToSTCD(uint8_t channel,edma_transfer_config_t *...
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** EDMA_DRV_ConfigSingleBlockTransfer - status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t...
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** EDMA_DRV_ConfigLoopTransfer - status_t EDMA_DRV_ConfigLoopTransfer(uint8_t channel,edma_transfer_config_t *...
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** EDMA_DRV_ConfigScatterGatherTransfer - status_t EDMA_DRV_ConfigScatterGatherTransfer(uint8_t...
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** EDMA_DRV_ConfigMultiBlockTransfer - status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t...
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** EDMA_DRV_CancelTransfer - void EDMA_DRV_CancelTransfer(bool error);
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** EDMA_DRV_SetChannelRequestAndTrigger - status_t EDMA_DRV_SetChannelRequestAndTrigger(uint8_t virtualChannel, uint8_t...
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** EDMA_DRV_ClearTCD - void EDMA_DRV_ClearTCD(uint8_t channel);
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** EDMA_DRV_SetSrcAddr - void EDMA_DRV_SetSrcAddr(uint8_t channel, uint32_t address);
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** EDMA_DRV_SetSrcOffset - void EDMA_DRV_SetSrcOffset(uint8_t channel, int16_t offset);
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** EDMA_DRV_SetSrcReadChunkSize - void EDMA_DRV_SetSrcReadChunkSize(uint8_t channel, edma_transfer_size_t size);
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** EDMA_DRV_SetDestAddr - void EDMA_DRV_SetDestAddr(uint8_t channel, uint32_t address);
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** EDMA_DRV_SetDestOffset - void EDMA_DRV_SetDestOffset(uint8_t channel, int16_t offset);
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** EDMA_DRV_SetDestWriteChunkSize - void EDMA_DRV_SetDestWriteChunkSize(uint8_t channel, edma_transfer_size_t size);
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** EDMA_DRV_SetMinorLoopBlockSize - void EDMA_DRV_SetMinorLoopBlockSize(uint8_t channel, uint32_t nbytes);
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** EDMA_DRV_SetMajorLoopIterationCount - void EDMA_DRV_SetMajorLoopIterationCount(uint8_t channel, uint32_t...
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** EDMA_DRV_GetRemainingMajorIterationsCount - uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t channel);
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** EDMA_DRV_SetScatterGatherLink - void EDMA_DRV_SetScatterGatherLink(uint8_t channel, uint32_t nextTCDAddr);
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** EDMA_DRV_DisableRequestsOnTransferComplete - void EDMA_DRV_DisableRequestsOnTransferComplete(uint8_t channel, bool disable);
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** EDMA_DRV_SetSrcLastAddrAdjustment - void EDMA_DRV_SetSrcLastAddrAdjustment(uint8_t channel, int32_t adjust);
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** EDMA_DRV_SetDestLastAddrAdjustment - void EDMA_DRV_SetDestLastAddrAdjustment(uint8_t channel, int32_t adjust);
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** EDMA_DRV_ConfigureInterrupt - void EDMA_DRV_ConfigureInterrupt(uint8_t channel, edma_channel_interrupt_t...
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** EDMA_DRV_TriggerSwRequest - void EDMA_DRV_TriggerSwRequest(uint8_t channel);
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**
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** Copyright 1997 - 2015 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** All Rights Reserved.
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**
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** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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** THE POSSIBILITY OF SUCH DAMAGE.
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** ###################################################################*/
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/*!
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** @file dmaController1.h
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** @version 01.00
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*/
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/*!
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** @addtogroup dmaController1_module dmaController1 module documentation
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** @{
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*/
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/* MODULE dmaController1
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*
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* @page misra_violations MISRA-C:2012 violations
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*
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* @section [global]
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* Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced.
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* The macros are defined to be used by application code.
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*/
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#ifndef dmaController1_H
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#define dmaController1_H
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/* Include inherited beans */
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#include "clockMan1.h"
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#include "Cpu.h"
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/*! @brief Physical channel number for channel configuration #0 */
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#define EDMA_CHN0_NUMBER 0U
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/*! @brief The total number of configured channels */
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#define EDMA_CONFIGURED_CHANNELS_COUNT 1U
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/*! @brief Driver state structure which holds driver runtime data */
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extern edma_state_t dmaController1_State;
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/*! @brief eDma channel state structure 0. Holds channel runtime data */
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extern edma_chn_state_t dmaController1Chn0_State;
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/*! @brief Array of channel state structures */
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extern edma_chn_state_t * const edmaChnStateArray[EDMA_CONFIGURED_CHANNELS_COUNT];
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/*! @brief eDma channel configuration 0 */
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extern edma_channel_config_t dmaController1Chn0_Config;
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/*! @brief Array of channel configuration structures */
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extern const edma_channel_config_t * const edmaChnConfigArray[EDMA_CONFIGURED_CHANNELS_COUNT];
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/*! @brief Configuration declaration */
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extern const edma_user_config_t dmaController1_InitConfig0;
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#endif /* ifndef dmaController1_H */
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/*!
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** @}
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*/
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/*
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** ###################################################################
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**
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** This file was created by Processor Expert 10.1 [05.21]
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** for the Freescale S32K series of microcontrollers.
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**
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** ###################################################################
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*/
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