S32K118_reva1_BaseDemo_LQFP48
Administrator
6
2021-09-16
Eclipse IDE
1.12.2.RT7_b1743-0713
main
Sources
Generated_Code
Documentation
Project_Settings
Generated_Code
3
3
3
true
false
true
0
false
false
true
false
true
12
true
false
true
CLASSIC
true
true
false
STANDALONE
${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0
SDK_S32K1xx_15
SDK_S32K1xx_15
SDK_S32K1xx_15
Referenced_Components
10
Beans
true
file:/${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0/tools/pex/Repositories/SDK_S32K1xx_15_Repository
S32K118_48
Cpu
7
true
ALWAYS_WRITE
CPU_CHIP2
01.197
false
DeviceName
false
false
Cpu
CPU
false
false
S32K118_48
SharedInternalProperties
1
SharedInternalPropertiesGrp
false
false
false
CPU_peripheral
false
false
CPU
false
CPUCond
1
SharedCpuMethodsInvisibleGroup
false
false
SystemInit
false
0
true
true
always
SystemInit
SystemCoreClockUpdate
false
0
true
true
always
SystemCoreClockUpdate
SystemSoftwareReset
false
0
true
true
always
SystemSoftwareReset
EventModule
false
false
Events
OnEvent
false
false
false
false
never
OnEventName
false
false
Cpu_OnEvent
L
0
GNU C Compiler
C_CompilerIdentificationLong
false
GNU C Compiler
true
PESLsupport
false
false
true
1
false
OSEKsupport
false
false
true
1
false
NotRapidGrp
false
true
UnhandledVectorsBehavior
false
false
true
0
true
UnhandledVectorsBehaviorFeatureGrp
false
true
UnhandledIntCode
false
(string list)
true
/* This code can be changed using the CPU component property "Build Options / Unhandled int code" */
PE_DEBUGHALT();
UserInitFeatureGrp
false
true
UserInitGrp
false
true
true
EntryPoint_UserDecl
false
(string list)
true
EntryPoint_UserCodeBefore
false
(string list)
true
EntryPoint_UserCodeAfter
false
(string list)
true
NotSdk0
false
true
Cmplr_GenerateDebuggerFiles
false
false
true
true
true
Cmplr_GenerateCfgFile
false
false
true
0
true
Cmplr_GenerateMemFile
false
false
true
0
true
Cmplr_GenerateXmlFile
false
false
true
0
true
Cmplr_AddStartupCond
false
true
NotSDK
false
true
Cmplr_AddStartupGrp
false
true
true
Cmplr_AddStartup
false
false
true
0
true
C_GenerateLINKFILE
false
false
true
false
false
InitializationState
false
Force_SetDefault
true
InterruptVectorTableSizeAdjustment
false
false
0
true
DEC
C_StackSize
false
false
1024
true
HEX
C_HeapSize
false
false
0
true
HEX
DefaultMemAreas
false
Click to set default >
true
C_AlraedyInitialized
false
false
true
1
false
SdkSettingsGrp
false
true
VectorTableCopyRam
false
false
true
0
true
DefaultMemInterrupts
false
false
true
2
INTERNAL_FLASH
DefaultMemCode
false
false
true
2
INTERNAL_FLASH
DefaultMemData
false
false
true
0
INTERNAL_RAM
C_RomRamList
false
0
true
true
C_PECompilerSupportCondGrp
false
true
C_PECompilerSupport
false
true
true
C_ToolDir
false
C:\CodeWarrior for ColdFire V7.0\
true
C_GenerateMAKEFILE
false
false
true
0
true
asmgrp
false
true
true
C_DebugInfo
false
false
true
0
true
C_CCPars
false
true
lnkgrp
false
true
true
C_GenerateMapFile
false
false
true
true
true
C_GenerateMapFile_ListClosure
false
false
true
1
false
C_GenerateMapFile_ListUnusedObjects
false
false
true
1
false
C_GenerateMapFile_ListDWARFObjects
false
false
true
1
false
C_GenerateSFile
false
false
true
true
true
C_GenerateSFile_Sort
false
false
true
1
false
C_GenerateSFile_MaxLength
false
false
26
true
DEC
C_GenerateSFile_EOL
false
false
true
1
DOS
C_LINKPars
false
true
NonECLIGrp
false
true
SystemPathsGrp
false
0
true
true
UserPathsGrp
false
0
true
false
LibrariesGrp
false
0
true
false
UserDirectoriesGrp
false
0
true
false
GNUC_ARM_Directory
false
true
Ansi-C
0
HEX
HEX
HEX
HEX
S32K118_48
4
32.768000000000
6
FLASH
true
7
0
8
5
true
4
true
3
true
2
true
7
true
8
true
9
true
11
true
0
0
Optimizations
false
true
true
Not_for_MPC512x
false
true
O_NoRangeChck
false
false
true
1
false
O_NoEnableTest
false
false
true
1
false
O_NoSpeedTest
false
false
true
1
false
Not_for_MPC5500_MCF
false
true
O_PIB_full_Init
false
false
true
1
false
file:/${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0/tools/pex/Repositories/SDK_S32K1xx_15_Repository
com.freescale.processorexpert.ksdk.pinsettings
PinSettings
pin_mux
2
true
ALWAYS_WRITE
PERIPHINSP
1.2.0
false
DeviceName
false
false
pin_mux
PeriphDevice
false
false
PinSettings
false
Processor
false
false
S32K118_48
ProcessorSpecificItem
1
Beans\PinSettings\IncS32K118_48.item
PinConfig
false
false
true
Routing
false
false
true
ADC
false
false
true
ADC0_UserName
false
false
ADC0
ADC0_subgroup
false
false
true
ADC0_adc_se_0
false
false
<Automatic>
false
ADC0_adc_se_1
false
false
<Automatic>
false
ADC0_adc_se_3
false
false
<Automatic>
false
ADC0_adc_se_4
false
false
<Automatic>
false
ADC0_adc_se_5
false
false
<Automatic>
false
ADC0_adc_se_6
false
false
<Automatic>
false
ADC0_adc_se_7
false
false
<Automatic>
false
ADC0_adc_se_9
false
false
<Automatic>
false
ADC0_adc_se_10
false
false
<Automatic>
false
ADC0_adc_se_11
false
false
<Automatic>
false
ADC0_adc_se_12
false
false
<Automatic>
false
ADC0_adc_se_13
false
false
<Automatic>
false
ADC0_adc_se_14
false
false
<Automatic>
false
AIPS
false
false
true
AIPS_UserName
false
false
AIPS
CAN
false
false
true
CAN0_UserName
false
false
CAN0
CAN0_subgroup
false
false
true
CAN0_can_rx_rxd
false
false
PTE4
false
CAN0_can_tx_txd
false
false
PTE5
false
CMP
false
false
true
CMP0_UserName
false
false
CMP0
CMP0_subgroup
false
false
true
CMP0_cmp_in_0
false
false
<Automatic>
false
CMP0_cmp_in_1
false
false
<Automatic>
false
CMP0_cmp_in_2
false
false
<Automatic>
false
CMP0_cmp_in_3
false
false
<Automatic>
false
CMP0_cmp_in_4
false
false
<Automatic>
false
CMP0_cmp_in_5
false
false
<Automatic>
false
CMP0_cmp_out
false
false
<Automatic>
false
CMP0_cmp_rrt
false
false
<Automatic>
false
CMU_FC
false
false
true
CMU_FC_0_UserName
false
false
CMU_FC_0
CMU_FC_1_UserName
false
false
CMU_FC_1
CRC
false
false
true
CRC_UserName
false
false
CRC
CSE_PRAM
false
false
true
CSE_PRAM_UserName
false
false
CSE_PRAM
DMA
false
false
true
DMA_UserName
false
false
DMA
DMAMUX
false
false
true
DMAMUX_UserName
false
false
DMAMUX
EIM
false
false
true
EIM_UserName
false
false
EIM
ERM
false
false
true
ERM_UserName
false
false
ERM
FLEXIO
false
false
true
FLEXIO_UserName
false
false
FLEXIO
FLEXIO_subgroup
false
false
true
FLEXIO_fxio_d_0
false
false
<Automatic>
false
FLEXIO_fxio_d_1
false
false
<Automatic>
false
FLEXIO_fxio_d_2
false
false
<Automatic>
false
FLEXIO_fxio_d_3
false
false
<Automatic>
false
FLEXIO_fxio_d_4
false
false
<Automatic>
false
FLEXIO_fxio_d_5
false
false
<Automatic>
false
FLEXIO_fxio_d_6
false
false
<Automatic>
false
FLEXIO_fxio_d_7
false
false
<Automatic>
false
FTFC
false
false
true
FTFC_UserName
false
false
FTFC
FTM
false
false
true
FTM0_UserName
false
false
FTM0
FTM0_subgroup
false
false
true
FTM0_ftm_ch_0
false
false
<Automatic>
false
FTM0_ftm_ch_0_Dir
false
false
<Automatic>
FTM0_ftm_ch_1
false
false
<Automatic>
false
FTM0_ftm_ch_1_Dir
false
false
<Automatic>
FTM0_ftm_ch_2
false
false
<Automatic>
false
FTM0_ftm_ch_2_Dir
false
false
<Automatic>
FTM0_ftm_ch_3
false
false
<Automatic>
false
FTM0_ftm_ch_3_Dir
false
false
<Automatic>
FTM0_ftm_ch_4
false
false
<Automatic>
false
FTM0_ftm_ch_4_Dir
false
false
<Automatic>
FTM0_ftm_ch_5
false
false
<Automatic>
false
FTM0_ftm_ch_5_Dir
false
false
<Automatic>
FTM0_ftm_ch_6
false
false
<Automatic>
false
FTM0_ftm_ch_6_Dir
false
false
<Automatic>
FTM0_ftm_ch_7
false
false
<Automatic>
false
FTM0_ftm_ch_7_Dir
false
false
<Automatic>
FTM0_ftm_flt_2
false
false
<Automatic>
false
FTM0_ftm_tclk_0
false
false
<Automatic>
false
FTM0_ftm_tclk_1
false
false
<Automatic>
false
FTM0_ftm_tclk_2
false
false
<Automatic>
false
FTM1_UserName
false
false
FTM1
FTM1_subgroup
false
false
true
FTM1_ftm_ch_0
false
false
<Automatic>
false
FTM1_ftm_ch_0_Dir
false
false
<Automatic>
FTM1_ftm_ch_1
false
false
<Automatic>
false
FTM1_ftm_ch_1_Dir
false
false
<Automatic>
FTM1_ftm_ch_2
false
false
<Automatic>
false
FTM1_ftm_ch_2_Dir
false
false
<Automatic>
FTM1_ftm_ch_3
false
false
<Automatic>
false
FTM1_ftm_ch_3_Dir
false
false
<Automatic>
FTM1_ftm_ch_4
false
false
<Automatic>
false
FTM1_ftm_ch_4_Dir
false
false
<Automatic>
FTM1_ftm_ch_5
false
false
<Automatic>
false
FTM1_ftm_ch_5_Dir
false
false
<Automatic>
FTM1_ftm_ch_6
false
false
<Automatic>
false
FTM1_ftm_ch_6_Dir
false
false
<Automatic>
FTM1_ftm_ch_7
false
false
<Automatic>
false
FTM1_ftm_ch_7_Dir
false
false
<Automatic>
FTM1_ftm_flt_0
false
false
<Automatic>
false
FTM1_ftm_flt_1
false
false
<Automatic>
false
FTM1_ftm_flt_2
false
false
<Automatic>
false
FTM1_ftm_qd_pha
false
false
<Automatic>
false
FTM1_ftm_qd_phb
false
false
<Automatic>
false
GPIO
false
false
true
PTA_UserName
false
false
PTA
PTA_subgroup
false
false
true
PTA_port_0
false
false
<Automatic>
false
PTA_port_0_Dir
false
false
<Automatic>
PTA_port_1
false
false
<Automatic>
false
PTA_port_1_Dir
false
false
<Automatic>
PTA_port_2
false
false
<Automatic>
false
PTA_port_2_Dir
false
false
<Automatic>
PTA_port_3
false
false
<Automatic>
false
PTA_port_3_Dir
false
false
<Automatic>
PTA_port_4
false
false
<Automatic>
false
PTA_port_4_Dir
false
false
<Automatic>
PTA_port_5
false
false
<Automatic>
false
PTA_port_5_Dir
false
false
<Automatic>
PTA_port_7
false
false
<Automatic>
false
PTA_port_7_Dir
false
false
<Automatic>
PTA_port_10
false
false
<Automatic>
false
PTA_port_10_Dir
false
false
<Automatic>
PTA_port_11
false
false
<Automatic>
false
PTA_port_11_Dir
false
false
<Automatic>
PTA_port_12
false
false
<Automatic>
false
PTA_port_12_Dir
false
false
<Automatic>
PTA_port_13
false
false
<Automatic>
false
PTA_port_13_Dir
false
false
<Automatic>
PTB_UserName
false
false
PTB
PTB_subgroup
false
false
true
PTB_port_0
false
false
<Automatic>
false
PTB_port_0_Dir
false
false
<Automatic>
PTB_port_1
false
false
<Automatic>
false
PTB_port_1_Dir
false
false
<Automatic>
PTB_port_2
false
false
<Automatic>
false
PTB_port_2_Dir
false
false
<Automatic>
PTB_port_3
false
false
<Automatic>
false
PTB_port_3_Dir
false
false
<Automatic>
PTB_port_4
false
false
<Automatic>
false
PTB_port_4_Dir
false
false
<Automatic>
PTB_port_5
false
false
<Automatic>
false
PTB_port_5_Dir
false
false
<Automatic>
PTB_port_6
false
false
<Automatic>
false
PTB_port_6_Dir
false
false
<Automatic>
PTB_port_7
false
false
<Automatic>
false
PTB_port_7_Dir
false
false
<Automatic>
PTB_port_13
false
false
<Automatic>
false
PTB_port_13_Dir
false
false
<Automatic>
PTC_UserName
false
false
PTC
PTC_subgroup
false
false
true
PTC_port_1
false
false
<Automatic>
false
PTC_port_1_Dir
false
false
<Automatic>
PTC_port_2
false
false
<Automatic>
false
PTC_port_2_Dir
false
false
<Automatic>
PTC_port_3
false
false
<Automatic>
false
PTC_port_3_Dir
false
false
<Automatic>
PTC_port_4
false
false
<Automatic>
false
PTC_port_4_Dir
false
false
<Automatic>
PTC_port_5
false
false
<Automatic>
false
PTC_port_5_Dir
false
false
<Automatic>
PTC_port_6
false
false
<Automatic>
false
PTC_port_6_Dir
false
false
<Automatic>
PTC_port_7
false
false
<Automatic>
false
PTC_port_7_Dir
false
false
<Automatic>
PTC_port_8
false
false
<Automatic>
false
PTC_port_8_Dir
false
false
<Automatic>
PTC_port_9
false
false
<Automatic>
false
PTC_port_9_Dir
false
false
<Automatic>
PTC_port_14
false
false
PTC14
false
PTC_port_14_Dir
false
false
Input
PTC_port_15
false
false
PTC15
false
PTC_port_15_Dir
false
false
Input
PTC_port_16
false
false
PTC16
false
PTC_port_16_Dir
false
false
Input
PTD_UserName
false
false
PTD
PTD_subgroup
false
false
true
PTD_port_0
false
false
<Automatic>
false
PTD_port_0_Dir
false
false
<Automatic>
PTD_port_1
false
false
<Automatic>
false
PTD_port_1_Dir
false
false
<Automatic>
PTD_port_2
false
false
<Automatic>
false
PTD_port_2_Dir
false
false
<Automatic>
PTD_port_3
false
false
<Automatic>
false
PTD_port_3_Dir
false
false
<Automatic>
PTD_port_5
false
false
<Automatic>
false
PTD_port_5_Dir
false
false
<Automatic>
PTD_port_15
false
false
PTD15
false
PTD_port_15_Dir
false
false
Output
PTD_port_16
false
false
PTD16
false
PTD_port_16_Dir
false
false
Output
PTE_UserName
false
false
PTE
PTE_subgroup
false
false
true
PTE_port_4
false
false
<Automatic>
false
PTE_port_4_Dir
false
false
<Automatic>
PTE_port_5
false
false
<Automatic>
false
PTE_port_5_Dir
false
false
<Automatic>
PTE_port_8
false
false
PTE8
false
PTE_port_8_Dir
false
false
Output
PTE_port_9
false
false
PTE9
false
PTE_port_9_Dir
false
false
Output
JTAG
false
false
true
JTAG_subgroup
false
false
true
JTAG_jtag_tclk
false
false
<Automatic>
false
JTAG_jtag_tdi
false
false
<Automatic>
false
JTAG_jtag_tdo
false
false
<Automatic>
false
JTAG_jtag_tms
false
false
<Automatic>
false
LMEM
false
false
true
LMEM_UserName
false
false
LMEM
LPI2C
false
false
true
LPI2C0_UserName
false
false
LPI2C0
LPI2C0_subgroup
false
false
true
LPI2C0_lpi2c_scl_scl
false
false
PTB7
false
LPI2C0_lpi2c_scls_scls
false
false
<Automatic>
false
LPI2C0_lpi2c_sda_sda
false
false
PTB6
false
LPI2C0_lpi2c_sdas_sdas
false
false
<Automatic>
false
LPIT
false
false
true
LPIT0_UserName
false
false
LPIT0
LPSPI
false
false
true
LPSPI0_UserName
false
false
LPSPI0
LPSPI0_subgroup
false
false
true
LPSPI0_lpspi_pcs_0
false
false
<Automatic>
false
LPSPI0_lpspi_pcs_0_Dir
false
false
<Automatic>
LPSPI0_lpspi_pcs_1
false
false
PTB5
false
LPSPI0_lpspi_pcs_1_Dir
false
false
Output
LPSPI0_lpspi_sck_sck
false
false
PTB2
false
LPSPI0_lpspi_sck_sck_Dir
false
false
Output
LPSPI0_lpspi_sin
false
false
PTB3
false
LPSPI0_lpspi_sin_Dir
false
false
Input
LPSPI0_lpspi_sout
false
false
PTB4
false
LPSPI0_lpspi_sout_Dir
false
false
Output
LPSPI1_UserName
false
false
LPSPI1
LPSPI1_subgroup
false
false
true
LPSPI1_lpspi_pcs_0
false
false
<Automatic>
false
LPSPI1_lpspi_pcs_0_Dir
false
false
<Automatic>
LPSPI1_lpspi_sck_sck
false
false
<Automatic>
false
LPSPI1_lpspi_sck_sck_Dir
false
false
<Automatic>
LPSPI1_lpspi_sin
false
false
<Automatic>
false
LPSPI1_lpspi_sin_Dir
false
false
<Automatic>
LPSPI1_lpspi_sout
false
false
<Automatic>
false
LPSPI1_lpspi_sout_Dir
false
false
<Automatic>
LPTMR
false
false
true
LPTMR0_UserName
false
false
LPTMR0
LPTMR0_subgroup
false
false
true
LPTMR0_lptmr_alt_2
false
false
<Automatic>
false
LPTMR0_lptmr_alt_3
false
false
<Automatic>
false
LPUART
false
false
true
LPUART0_UserName
false
false
LPUART0
LPUART0_subgroup
false
false
true
LPUART0_lpuart_cts
false
false
<Automatic>
false
LPUART0_lpuart_rts
false
false
<Automatic>
false
LPUART0_lpuart_rx
false
false
PTB0
false
LPUART0_lpuart_tx
false
false
PTB1
false
LPUART0_lpuart_tx_Dir
false
false
<Automatic>
LPUART1_UserName
false
false
LPUART1
LPUART1_subgroup
false
false
true
LPUART1_lpuart_rts
false
false
<Automatic>
false
LPUART1_lpuart_rx
false
false
PTC6
false
LPUART1_lpuart_tx
false
false
PTC7
false
LPUART1_lpuart_tx_Dir
false
false
Output
MCM
false
false
true
MCM_UserName
false
false
MCM
MPU
false
false
true
MPU_UserName
false
false
MPU
MSCM
false
false
true
MSCM_UserName
false
false
MSCM
OSC
false
false
true
PCC
false
false
true
PCC_UserName
false
false
PCC
PDB
false
false
true
PDB0_UserName
false
false
PDB0
PMC
false
false
true
PMC_UserName
false
false
PMC
PORT
false
false
true
PORTA_UserName
false
false
PORTA
PORTB_UserName
false
false
PORTB
PORTC_UserName
false
false
PORTC
PORTD_UserName
false
false
PORTD
PORTE_UserName
false
false
PORTE
Platform
false
false
true
Platform_subgroup
false
false
true
Platform_clkout_18
false
false
<Automatic>
false
Platform_nmi_b_45
false
false
<Automatic>
false
Platform_reset_b_63
false
false
<Automatic>
false
PowerAndGround
false
false
true
PowerAndGround_subgroup
false
false
true
PowerAndGround_VDD_7
VDD7
false
PowerAndGround_VDD_41
VDD41
false
PowerAndGround_VDDA_8
VDDA
false
PowerAndGround_VSS_10
VSS10
false
PowerAndGround_VSS_40
VSS40
false
RCM
false
false
true
RCM_UserName
false
false
RCM
RTC
false
false
true
RTC_UserName
false
false
RTC
RTC_subgroup
false
false
true
RTC_rtc_clkin
false
false
<Automatic>
false
RTC_rtc_clkout
false
false
<Automatic>
false
S32_NVIC
false
false
true
S32_SCB
false
false
true
S32_SCB_UserName
false
false
S32_SCB
S32_SysTick
false
false
true
S32_SysTick_UserName
false
false
S32_SysTick
SCG
false
false
true
SCG_UserName
false
false
SCG
SIM
false
false
true
SIM_UserName
false
false
SIM
SMC
false
false
true
SMC_UserName
false
false
SMC
SWD
false
false
true
SWD_subgroup
false
false
true
SWD_swd_clk
false
false
<Automatic>
false
SWD_swd_dio
false
false
<Automatic>
false
TRGMUX
false
false
true
TRGMUX_UserName
false
false
TRGMUX
TRGMUX_subgroup
false
false
true
TRGMUX_trg_in_0
false
false
<Automatic>
false
TRGMUX_trg_in_1
false
false
<Automatic>
false
TRGMUX_trg_in_2
false
false
<Automatic>
false
TRGMUX_trg_in_3
false
false
<Automatic>
false
TRGMUX_trg_in_4
false
false
<Automatic>
false
TRGMUX_trg_in_5
false
false
<Automatic>
false
TRGMUX_trg_in_7
false
false
<Automatic>
false
TRGMUX_trg_in_8
false
false
<Automatic>
false
TRGMUX_trg_in_9
false
false
<Automatic>
false
TRGMUX_trg_out_0
false
false
<Automatic>
false
TRGMUX_trg_out_1
false
false
<Automatic>
false
TRGMUX_trg_out_2
false
false
<Automatic>
false
TRGMUX_trg_out_3
false
false
<Automatic>
false
WDOG
false
false
true
WDOG_UserName
false
false
WDOG
special
false
false
true
ElectricalProperties
false
false
true
PTD1
false
false
true
PTD1_UserName
false
false
PTD1
PTD1_ISF
false
false
<Automatic>
<Automatic>
PTD1_IRQC
false
false
<Automatic>
<Automatic>
PTD1_MUX
false
false
<Automatic>
<Automatic>
PTD1_LK
false
false
<Automatic>
<Automatic>
PTD1_DSE
false
false
<Automatic>
<Automatic>
PTD1_PE
false
false
<Automatic>
<Automatic>
PTD1_PS
false
false
<Automatic>
<Automatic>
PTD1_InitValue
false
false
<Automatic>
<Automatic>
PTD1_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD0
false
false
true
PTD0_UserName
false
false
PTD0
PTD0_ISF
false
false
<Automatic>
<Automatic>
PTD0_IRQC
false
false
<Automatic>
<Automatic>
PTD0_MUX
false
false
<Automatic>
<Automatic>
PTD0_LK
false
false
<Automatic>
<Automatic>
PTD0_DSE
false
false
<Automatic>
<Automatic>
PTD0_PE
false
false
<Automatic>
<Automatic>
PTD0_PS
false
false
<Automatic>
<Automatic>
PTD0_InitValue
false
false
<Automatic>
<Automatic>
PTD0_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE5
false
false
true
PTE5_UserName
false
false
PTE5
PTE5_ISF
false
false
<Automatic>
<Automatic>
PTE5_IRQC
false
false
<Automatic>
<Automatic>
PTE5_MUX
false
false
<Automatic>
<Automatic>
PTE5_LK
false
false
<Automatic>
<Automatic>
PTE5_PE
false
false
<Automatic>
<Automatic>
PTE5_PS
false
false
<Automatic>
<Automatic>
PTE5_InitValue
false
false
<Automatic>
<Automatic>
PTE5_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE4
false
false
true
PTE4_UserName
false
false
PTE4
PTE4_ISF
false
false
<Automatic>
<Automatic>
PTE4_IRQC
false
false
<Automatic>
<Automatic>
PTE4_MUX
false
false
<Automatic>
<Automatic>
PTE4_LK
false
false
<Automatic>
<Automatic>
PTE4_DSE
false
false
<Automatic>
<Automatic>
PTE4_PE
false
false
<Automatic>
<Automatic>
PTE4_PS
false
false
<Automatic>
<Automatic>
PTE4_InitValue
false
false
<Automatic>
<Automatic>
PTE4_DigitalFilter
false
false
<Automatic>
<Automatic>
VDD7
false
false
true
VDD7_UserName
false
false
VDD7
VDDA
false
false
true
VDDA_UserName
false
false
VDDA
VSS10
false
false
true
VSS10_UserName
false
false
VSS10
PTB7
false
false
true
PTB7_UserName
false
false
PTB7
PTB7_ISF
false
false
<Automatic>
<Automatic>
PTB7_IRQC
false
false
<Automatic>
<Automatic>
PTB7_MUX
false
false
<Automatic>
<Automatic>
PTB7_LK
false
false
<Automatic>
<Automatic>
PTB7_PE
false
false
<Automatic>
<Automatic>
PTB7_PS
false
false
<Automatic>
<Automatic>
PTB7_InitValue
false
false
<Automatic>
<Automatic>
PTB7_DigitalFilter
false
false
<Automatic>
<Automatic>
PTB6
false
false
true
PTB6_UserName
false
false
PTB6
PTB6_ISF
false
false
<Automatic>
<Automatic>
PTB6_IRQC
false
false
<Automatic>
<Automatic>
PTB6_MUX
false
false
<Automatic>
<Automatic>
PTB6_LK
false
false
<Automatic>
<Automatic>
PTB6_DSE
false
false
<Automatic>
<Automatic>
PTB6_PE
false
false
<Automatic>
<Automatic>
PTB6_PS
false
false
<Automatic>
<Automatic>
PTB6_InitValue
false
false
<Automatic>
<Automatic>
PTB6_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD16
false
false
true
PTD16_UserName
false
false
PTD16
PTD16_ISF
false
false
<Automatic>
<Automatic>
PTD16_IRQC
false
false
<Automatic>
<Automatic>
PTD16_MUX
false
false
<Automatic>
<Automatic>
PTD16_LK
false
false
<Automatic>
<Automatic>
PTD16_DSE
false
false
<Automatic>
<Automatic>
PTD16_PE
false
false
<Automatic>
<Automatic>
PTD16_PS
false
false
<Automatic>
<Automatic>
PTD16_InitValue
false
false
<Automatic>
<Automatic>
PTD16_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD15
false
false
true
PTD15_UserName
false
false
PTD15
PTD15_ISF
false
false
<Automatic>
<Automatic>
PTD15_IRQC
false
false
<Automatic>
<Automatic>
PTD15_MUX
false
false
<Automatic>
<Automatic>
PTD15_LK
false
false
<Automatic>
<Automatic>
PTD15_DSE
false
false
<Automatic>
<Automatic>
PTD15_PE
false
false
<Automatic>
<Automatic>
PTD15_PS
false
false
<Automatic>
<Automatic>
PTD15_InitValue
false
false
<Automatic>
<Automatic>
PTD15_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE9
false
false
true
PTE9_UserName
false
false
PTE9
PTE9_ISF
false
false
<Automatic>
<Automatic>
PTE9_IRQC
false
false
<Automatic>
<Automatic>
PTE9_MUX
false
false
<Automatic>
<Automatic>
PTE9_LK
false
false
<Automatic>
<Automatic>
PTE9_PE
false
false
<Automatic>
<Automatic>
PTE9_PS
false
false
<Automatic>
<Automatic>
PTE9_InitValue
false
false
<Automatic>
<Automatic>
PTE9_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE8
false
false
true
PTE8_UserName
false
false
PTE8
PTE8_ISF
false
false
<Automatic>
<Automatic>
PTE8_IRQC
false
false
<Automatic>
<Automatic>
PTE8_MUX
false
false
<Automatic>
<Automatic>
PTE8_LK
false
false
<Automatic>
<Automatic>
PTE8_PE
false
false
<Automatic>
<Automatic>
PTE8_PS
false
false
<Automatic>
<Automatic>
PTE8_InitValue
false
false
<Automatic>
<Automatic>
PTE8_DigitalFilter
false
false
<Automatic>
<Automatic>
PTB5
false
false
true
PTB5_UserName
false
false
PTB5
PTB5_ISF
false
false
<Automatic>
<Automatic>
PTB5_IRQC
false
false
<Automatic>
<Automatic>
PTB5_MUX
false
false
<Automatic>
<Automatic>
PTB5_LK
false
false
<Automatic>
<Automatic>
PTB5_DSE
false
false
<Automatic>
<Automatic>
PTB5_PE
false
false
<Automatic>
<Automatic>
PTB5_PS
false
false
<Automatic>
<Automatic>
PTB5_InitValue
false
false
<Automatic>
<Automatic>
PTB5_DigitalFilter
false
false
<Automatic>
<Automatic>
PTB4
false
false
true
PTB4_UserName
false
false
PTB4
PTB4_ISF
false
false
<Automatic>
<Automatic>
PTB4_IRQC
false
false
<Automatic>
<Automatic>
PTB4_MUX
false
false
<Automatic>
<Automatic>
PTB4_LK
false
false
<Automatic>
<Automatic>
PTB4_DSE
false
false
<Automatic>
<Automatic>
PTB4_PE
false
false
<Automatic>
<Automatic>
PTB4_PS
false
false
<Automatic>
<Automatic>
PTB4_InitValue
false
false
<Automatic>
<Automatic>
PTB4_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC3
false
false
true
PTC3_UserName
false
false
PTC3
PTC3_ISF
false
false
<Automatic>
<Automatic>
PTC3_IRQC
false
false
<Automatic>
<Automatic>
PTC3_MUX
false
false
<Automatic>
<Automatic>
PTC3_LK
false
false
<Automatic>
<Automatic>
PTC3_PE
false
false
<Automatic>
<Automatic>
PTC3_PS
false
false
<Automatic>
<Automatic>
PTC3_InitValue
false
false
<Automatic>
<Automatic>
PTC3_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC2
false
false
true
PTC2_UserName
false
false
PTC2
PTC2_ISF
false
false
<Automatic>
<Automatic>
PTC2_IRQC
false
false
<Automatic>
<Automatic>
PTC2_MUX
false
false
<Automatic>
<Automatic>
PTC2_LK
false
false
<Automatic>
<Automatic>
PTC2_PE
false
false
<Automatic>
<Automatic>
PTC2_PS
false
false
<Automatic>
<Automatic>
PTC2_InitValue
false
false
<Automatic>
<Automatic>
PTC2_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD5
false
false
true
PTD5_UserName
false
false
PTD5
PTD5_ISF
false
false
<Automatic>
<Automatic>
PTD5_IRQC
false
false
<Automatic>
<Automatic>
PTD5_MUX
false
false
<Automatic>
<Automatic>
PTD5_LK
false
false
<Automatic>
<Automatic>
PTD5_PE
false
false
<Automatic>
<Automatic>
PTD5_PS
false
false
<Automatic>
<Automatic>
PTD5_InitValue
false
false
<Automatic>
<Automatic>
PTD5_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC1
false
false
true
PTC1_UserName
false
false
PTC1
PTC1_ISF
false
false
<Automatic>
<Automatic>
PTC1_IRQC
false
false
<Automatic>
<Automatic>
PTC1_MUX
false
false
<Automatic>
<Automatic>
PTC1_LK
false
false
<Automatic>
<Automatic>
PTC1_PE
false
false
<Automatic>
<Automatic>
PTC1_PS
false
false
<Automatic>
<Automatic>
PTC1_InitValue
false
false
<Automatic>
<Automatic>
PTC1_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC16
false
false
true
PTC16_UserName
false
false
PTC16
PTC16_ISF
false
false
<Automatic>
<Automatic>
PTC16_IRQC
false
false
<Automatic>
<Automatic>
PTC16_MUX
false
false
<Automatic>
<Automatic>
PTC16_LK
false
false
<Automatic>
<Automatic>
PTC16_PE
false
false
<Automatic>
<Automatic>
PTC16_PS
false
false
<Automatic>
<Automatic>
PTC16_InitValue
false
false
<Automatic>
<Automatic>
PTC16_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC15
false
false
true
PTC15_UserName
false
false
PTC15
PTC15_ISF
false
false
<Automatic>
<Automatic>
PTC15_IRQC
false
false
<Automatic>
<Automatic>
PTC15_MUX
false
false
<Automatic>
<Automatic>
PTC15_LK
false
false
<Automatic>
<Automatic>
PTC15_PE
false
false
<Automatic>
<Automatic>
PTC15_PS
false
false
<Automatic>
<Automatic>
PTC15_InitValue
false
false
<Automatic>
<Automatic>
PTC15_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC14
false
false
true
PTC14_UserName
false
false
PTC14
PTC14_ISF
false
false
<Automatic>
<Automatic>
PTC14_IRQC
false
false
<Automatic>
<Automatic>
PTC14_MUX
false
false
<Automatic>
<Automatic>
PTC14_LK
false
false
<Automatic>
<Automatic>
PTC14_PE
false
false
<Automatic>
<Automatic>
PTC14_PS
false
false
<Automatic>
<Automatic>
PTC14_InitValue
false
false
<Automatic>
<Automatic>
PTC14_DigitalFilter
false
false
<Automatic>
<Automatic>
PTB3
false
false
true
PTB3_UserName
false
false
PTB3
PTB3_ISF
false
false
<Automatic>
<Automatic>
PTB3_IRQC
false
false
<Automatic>
<Automatic>
PTB3_MUX
false
false
<Automatic>
<Automatic>
PTB3_LK
false
false
<Automatic>
<Automatic>
PTB3_PE
false
false
<Automatic>
<Automatic>
PTB3_PS
false
false
<Automatic>
<Automatic>
PTB3_InitValue
false
false
<Automatic>
<Automatic>
PTB3_DigitalFilter
false
false
<Automatic>
<Automatic>
PTB2
false
false
true
PTB2_UserName
false
false
PTB2
PTB2_ISF
false
false
<Automatic>
<Automatic>
PTB2_IRQC
false
false
<Automatic>
<Automatic>
PTB2_MUX
false
false
<Automatic>
<Automatic>
PTB2_LK
false
false
<Automatic>
<Automatic>
PTB2_PE
false
false
<Automatic>
<Automatic>
PTB2_PS
false
false
<Automatic>
<Automatic>
PTB2_InitValue
false
false
<Automatic>
<Automatic>
PTB2_DigitalFilter
false
false
<Automatic>
<Automatic>
PTB1
false
false
true
PTB1_UserName
false
false
PTB1
PTB1_ISF
false
false
<Automatic>
<Automatic>
PTB1_IRQC
false
false
<Automatic>
<Automatic>
PTB1_MUX
false
false
<Automatic>
<Automatic>
PTB1_LK
false
false
<Automatic>
<Automatic>
PTB1_PE
false
false
<Automatic>
<Automatic>
PTB1_PS
false
false
<Automatic>
<Automatic>
PTB1_InitValue
false
false
<Automatic>
<Automatic>
PTB1_DigitalFilter
false
false
<Automatic>
<Automatic>
PTB0
false
false
true
PTB0_UserName
false
false
PTB0
PTB0_ISF
false
false
<Automatic>
<Automatic>
PTB0_IRQC
false
false
<Automatic>
<Automatic>
PTB0_MUX
false
false
<Automatic>
<Automatic>
PTB0_LK
false
false
<Automatic>
<Automatic>
PTB0_PE
false
false
<Automatic>
<Automatic>
PTB0_PS
false
false
<Automatic>
<Automatic>
PTB0_InitValue
false
false
<Automatic>
<Automatic>
PTB0_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC9
false
false
true
PTC9_UserName
false
false
PTC9
PTC9_ISF
false
false
<Automatic>
<Automatic>
PTC9_IRQC
false
false
<Automatic>
<Automatic>
PTC9_MUX
false
false
<Automatic>
<Automatic>
PTC9_LK
false
false
<Automatic>
<Automatic>
PTC9_PE
false
false
<Automatic>
<Automatic>
PTC9_PS
false
false
<Automatic>
<Automatic>
PTC9_InitValue
false
false
<Automatic>
<Automatic>
PTC9_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC8
false
false
true
PTC8_UserName
false
false
PTC8
PTC8_ISF
false
false
<Automatic>
<Automatic>
PTC8_IRQC
false
false
<Automatic>
<Automatic>
PTC8_MUX
false
false
<Automatic>
<Automatic>
PTC8_LK
false
false
<Automatic>
<Automatic>
PTC8_PE
false
false
<Automatic>
<Automatic>
PTC8_PS
false
false
<Automatic>
<Automatic>
PTC8_InitValue
false
false
<Automatic>
<Automatic>
PTC8_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA7
false
false
true
PTA7_UserName
false
false
PTA7
PTA7_ISF
false
false
<Automatic>
<Automatic>
PTA7_IRQC
false
false
<Automatic>
<Automatic>
PTA7_MUX
false
false
<Automatic>
<Automatic>
PTA7_LK
false
false
<Automatic>
<Automatic>
PTA7_PE
false
false
<Automatic>
<Automatic>
PTA7_PS
false
false
<Automatic>
<Automatic>
PTA7_InitValue
false
false
<Automatic>
<Automatic>
PTA7_DigitalFilter
false
false
<Automatic>
<Automatic>
VSS40
false
false
true
VSS40_UserName
false
false
VSS40
VDD41
false
false
true
VDD41_UserName
false
false
VDD41
PTB13
false
false
true
PTB13_UserName
false
false
PTB13
PTB13_ISF
false
false
<Automatic>
<Automatic>
PTB13_IRQC
false
false
<Automatic>
<Automatic>
PTB13_MUX
false
false
<Automatic>
<Automatic>
PTB13_LK
false
false
<Automatic>
<Automatic>
PTB13_PE
false
false
<Automatic>
<Automatic>
PTB13_PS
false
false
<Automatic>
<Automatic>
PTB13_InitValue
false
false
<Automatic>
<Automatic>
PTB13_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD3
false
false
true
PTD3_UserName
false
false
PTD3
PTD3_ISF
false
false
<Automatic>
<Automatic>
PTD3_IRQC
false
false
<Automatic>
<Automatic>
PTD3_MUX
false
false
<Automatic>
<Automatic>
PTD3_LK
false
false
<Automatic>
<Automatic>
PTD3_PFE
false
false
<Automatic>
<Automatic>
PTD3_PE
false
false
<Automatic>
<Automatic>
PTD3_PS
false
false
<Automatic>
<Automatic>
PTD3_InitValue
false
false
<Automatic>
<Automatic>
PTD3_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD2
false
false
true
PTD2_UserName
false
false
PTD2
PTD2_ISF
false
false
<Automatic>
<Automatic>
PTD2_IRQC
false
false
<Automatic>
<Automatic>
PTD2_MUX
false
false
<Automatic>
<Automatic>
PTD2_LK
false
false
<Automatic>
<Automatic>
PTD2_PE
false
false
<Automatic>
<Automatic>
PTD2_PS
false
false
<Automatic>
<Automatic>
PTD2_InitValue
false
false
<Automatic>
<Automatic>
PTD2_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA3
false
false
true
PTA3_UserName
false
false
PTA3
PTA3_ISF
false
false
<Automatic>
<Automatic>
PTA3_IRQC
false
false
<Automatic>
<Automatic>
PTA3_MUX
false
false
<Automatic>
<Automatic>
PTA3_LK
false
false
<Automatic>
<Automatic>
PTA3_PE
false
false
<Automatic>
<Automatic>
PTA3_PS
false
false
<Automatic>
<Automatic>
PTA3_InitValue
false
false
<Automatic>
<Automatic>
PTA3_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA2
false
false
true
PTA2_UserName
false
false
PTA2
PTA2_ISF
false
false
<Automatic>
<Automatic>
PTA2_IRQC
false
false
<Automatic>
<Automatic>
PTA2_MUX
false
false
<Automatic>
<Automatic>
PTA2_LK
false
false
<Automatic>
<Automatic>
PTA2_PE
false
false
<Automatic>
<Automatic>
PTA2_PS
false
false
<Automatic>
<Automatic>
PTA2_InitValue
false
false
<Automatic>
<Automatic>
PTA2_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA1
false
false
true
PTA1_UserName
false
false
PTA1
PTA1_ISF
false
false
<Automatic>
<Automatic>
PTA1_IRQC
false
false
<Automatic>
<Automatic>
PTA1_MUX
false
false
<Automatic>
<Automatic>
PTA1_LK
false
false
<Automatic>
<Automatic>
PTA1_PE
false
false
<Automatic>
<Automatic>
PTA1_PS
false
false
<Automatic>
<Automatic>
PTA1_InitValue
false
false
<Automatic>
<Automatic>
PTA1_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA0
false
false
true
PTA0_UserName
false
false
PTA0
PTA0_ISF
false
false
<Automatic>
<Automatic>
PTA0_IRQC
false
false
<Automatic>
<Automatic>
PTA0_MUX
false
false
<Automatic>
<Automatic>
PTA0_LK
false
false
<Automatic>
<Automatic>
PTA0_PE
false
false
<Automatic>
<Automatic>
PTA0_PS
false
false
<Automatic>
<Automatic>
PTA0_InitValue
false
false
<Automatic>
<Automatic>
PTA0_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC7
false
false
true
PTC7_UserName
false
false
PTC7
PTC7_ISF
false
false
<Automatic>
<Automatic>
PTC7_IRQC
false
false
<Automatic>
<Automatic>
PTC7_MUX
false
false
<Automatic>
<Automatic>
PTC7_LK
false
false
<Automatic>
<Automatic>
PTC7_PE
false
false
<Automatic>
<Automatic>
PTC7_PS
false
false
<Automatic>
<Automatic>
PTC7_InitValue
false
false
<Automatic>
<Automatic>
PTC7_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC6
false
false
true
PTC6_UserName
false
false
PTC6
PTC6_ISF
false
false
<Automatic>
<Automatic>
PTC6_IRQC
false
false
<Automatic>
<Automatic>
PTC6_MUX
false
false
<Automatic>
<Automatic>
PTC6_LK
false
false
<Automatic>
<Automatic>
PTC6_PE
false
false
<Automatic>
<Automatic>
PTC6_PS
false
false
<Automatic>
<Automatic>
PTC6_InitValue
false
false
<Automatic>
<Automatic>
PTC6_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA13
false
false
true
PTA13_UserName
false
false
PTA13
PTA13_ISF
false
false
<Automatic>
<Automatic>
PTA13_IRQC
false
false
<Automatic>
<Automatic>
PTA13_MUX
false
false
<Automatic>
<Automatic>
PTA13_LK
false
false
<Automatic>
<Automatic>
PTA13_PE
false
false
<Automatic>
<Automatic>
PTA13_PS
false
false
<Automatic>
<Automatic>
PTA13_InitValue
false
false
<Automatic>
<Automatic>
PTA13_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA12
false
false
true
PTA12_UserName
false
false
PTA12
PTA12_ISF
false
false
<Automatic>
<Automatic>
PTA12_IRQC
false
false
<Automatic>
<Automatic>
PTA12_MUX
false
false
<Automatic>
<Automatic>
PTA12_LK
false
false
<Automatic>
<Automatic>
PTA12_PE
false
false
<Automatic>
<Automatic>
PTA12_PS
false
false
<Automatic>
<Automatic>
PTA12_InitValue
false
false
<Automatic>
<Automatic>
PTA12_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA11
false
false
true
PTA11_UserName
false
false
PTA11
PTA11_ISF
false
false
<Automatic>
<Automatic>
PTA11_IRQC
false
false
<Automatic>
<Automatic>
PTA11_MUX
false
false
<Automatic>
<Automatic>
PTA11_LK
false
false
<Automatic>
<Automatic>
PTA11_PE
false
false
<Automatic>
<Automatic>
PTA11_PS
false
false
<Automatic>
<Automatic>
PTA11_InitValue
false
false
<Automatic>
<Automatic>
PTA11_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA10
false
false
true
PTA10_UserName
false
false
PTA10
PTA10_ISF
false
false
<Automatic>
<Automatic>
PTA10_IRQC
false
false
<Automatic>
<Automatic>
PTA10_MUX
false
false
<Automatic>
<Automatic>
PTA10_LK
false
false
<Automatic>
<Automatic>
PTA10_DSE
false
false
<Automatic>
<Automatic>
PTA10_PE
false
false
<Automatic>
<Automatic>
PTA10_PS
false
false
<Automatic>
<Automatic>
PTA10_InitValue
false
false
<Automatic>
<Automatic>
PTA10_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC5
false
false
true
PTC5_UserName
false
false
PTC5
PTC5_ISF
false
false
<Automatic>
<Automatic>
PTC5_IRQC
false
false
<Automatic>
<Automatic>
PTC5_MUX
false
false
<Automatic>
<Automatic>
PTC5_LK
false
false
<Automatic>
<Automatic>
PTC5_PE
false
false
<Automatic>
<Automatic>
PTC5_PS
false
false
<Automatic>
<Automatic>
PTC5_InitValue
false
false
<Automatic>
<Automatic>
PTC5_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC4
false
false
true
PTC4_UserName
false
false
PTC4
PTC4_ISF
false
false
<Automatic>
<Automatic>
PTC4_IRQC
false
false
<Automatic>
<Automatic>
PTC4_MUX
false
false
<Automatic>
<Automatic>
PTC4_LK
false
false
<Automatic>
<Automatic>
PTC4_PE
false
false
<Automatic>
<Automatic>
PTC4_PS
false
false
<Automatic>
<Automatic>
PTC4_InitValue
false
false
<Automatic>
<Automatic>
PTC4_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA5
false
false
true
PTA5_UserName
false
false
PTA5
PTA5_ISF
false
false
<Automatic>
<Automatic>
PTA5_IRQC
false
false
<Automatic>
<Automatic>
PTA5_MUX
false
false
<Automatic>
<Automatic>
PTA5_LK
false
false
<Automatic>
<Automatic>
PTA5_PFE
false
false
<Automatic>
<Automatic>
PTA5_PE
false
false
<Automatic>
<Automatic>
PTA5_PS
false
false
<Automatic>
<Automatic>
PTA5_InitValue
false
false
<Automatic>
<Automatic>
PTA5_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA4
false
false
true
PTA4_UserName
false
false
PTA4
PTA4_ISF
false
false
<Automatic>
<Automatic>
PTA4_IRQC
false
false
<Automatic>
<Automatic>
PTA4_MUX
false
false
<Automatic>
<Automatic>
PTA4_LK
false
false
<Automatic>
<Automatic>
PTA4_PE
false
false
<Automatic>
<Automatic>
PTA4_PS
false
false
<Automatic>
<Automatic>
PTA4_InitValue
false
false
<Automatic>
<Automatic>
PTA4_DigitalFilter
false
false
<Automatic>
<Automatic>
SettingsGrp
false
false
Settings
false
false
true
SdkSpecificPinSettings
1
Beans\PinSettings\Items\S32K144_SDK01\PinSettings.item
HALGrp
false
false
true
UtilizeResetValuesCondGroup
false
false
UtilizeResetValues
false
false
false
0
yes
LinkGrp
false
false
true
Link0
false
false
clockMan1
ADC0_adc_se_2
false
false
<Automatic>
false
ADC0_adc_se_8
false
false
<Automatic>
false
ADC0_adc_se_15
false
false
<Automatic>
false
CMP0_cmp_in_6
false
false
<Automatic>
false
CMP0_cmp_in_7
false
false
<Automatic>
false
FTM0_ftm_flt_0
false
false
<Automatic>
false
FTM0_ftm_flt_1
false
false
<Automatic>
false
FTM0_ftm_flt_3
false
false
<Automatic>
false
FTM1_ftm_flt_3
false
false
<Automatic>
false
PTA_port_6
false
false
<Automatic>
false
PTA_port_6_Dir
false
false
<Automatic>
PTB_port_12
false
false
<Automatic>
false
PTB_port_12_Dir
false
false
<Automatic>
PTC_port_0
false
false
<Automatic>
false
PTC_port_0_Dir
false
false
<Automatic>
PTC_port_17
false
false
<Automatic>
false
PTC_port_17_Dir
false
false
<Automatic>
PTD_port_4
false
false
<Automatic>
false
PTD_port_4_Dir
false
false
<Automatic>
PTD_port_6
false
false
<Automatic>
false
PTD_port_6_Dir
false
false
<Automatic>
PTD_port_7
false
false
<Automatic>
false
PTD_port_7_Dir
false
false
<Automatic>
PTE_port_0
false
false
<Automatic>
false
PTE_port_0_Dir
false
false
<Automatic>
PTE_port_1
false
false
<Automatic>
false
PTE_port_1_Dir
false
false
<Automatic>
PTE_port_2
false
false
<Automatic>
false
PTE_port_2_Dir
false
false
<Automatic>
PTE_port_3
false
false
<Automatic>
false
PTE_port_3_Dir
false
false
<Automatic>
PTE_port_6
false
false
<Automatic>
false
PTE_port_6_Dir
false
false
<Automatic>
PTE_port_7
false
false
<Automatic>
false
PTE_port_7_Dir
false
false
<Automatic>
PTE_port_10
false
false
<Automatic>
false
PTE_port_10_Dir
false
false
<Automatic>
PTE_port_11
false
false
<Automatic>
false
PTE_port_11_Dir
false
false
<Automatic>
LPI2C0_lpi2c_hreq_hreq
false
false
<Automatic>
false
LPSPI0_lpspi_pcs_2
false
false
<Automatic>
false
LPSPI0_lpspi_pcs_2_Dir
false
false
<Automatic>
LPSPI1_lpspi_pcs_1
false
false
<Automatic>
false
LPSPI1_lpspi_pcs_1_Dir
false
false
<Automatic>
LPTMR0_lptmr_alt_1
false
false
<Automatic>
false
LPUART1_lpuart_cts
false
false
<Automatic>
false
Platform_clkout_4
false
false
<Automatic>
false
PowerAndGround_VREFH_9
VREFH
false
TRGMUX_trg_in_6
false
false
<Automatic>
false
TRGMUX_trg_out_4
false
false
<Automatic>
false
TRGMUX_trg_out_5
false
false
<Automatic>
false
PTE11
false
false
true
PTE11_UserName
false
false
PTE11
PTE11_ISF
false
false
<Automatic>
<Automatic>
PTE11_IRQC
false
false
<Automatic>
<Automatic>
PTE11_MUX
false
false
<Automatic>
<Automatic>
PTE11_LK
false
false
<Automatic>
<Automatic>
PTE11_PE
false
false
<Automatic>
<Automatic>
PTE11_PS
false
false
<Automatic>
<Automatic>
PTE11_InitValue
false
false
<Automatic>
<Automatic>
PTE11_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE10
false
false
true
PTE10_UserName
false
false
PTE10
PTE10_ISF
false
false
<Automatic>
<Automatic>
PTE10_IRQC
false
false
<Automatic>
<Automatic>
PTE10_MUX
false
false
<Automatic>
<Automatic>
PTE10_LK
false
false
<Automatic>
<Automatic>
PTE10_PE
false
false
<Automatic>
<Automatic>
PTE10_PS
false
false
<Automatic>
<Automatic>
PTE10_InitValue
false
false
<Automatic>
<Automatic>
PTE10_DigitalFilter
false
false
<Automatic>
<Automatic>
VREFH
false
false
true
VREFH_UserName
false
false
VREFH
PTE3
false
false
true
PTE3_UserName
false
false
PTE3
PTE3_ISF
false
false
<Automatic>
<Automatic>
PTE3_IRQC
false
false
<Automatic>
<Automatic>
PTE3_MUX
false
false
<Automatic>
<Automatic>
PTE3_LK
false
false
<Automatic>
<Automatic>
PTE3_PE
false
false
<Automatic>
<Automatic>
PTE3_PS
false
false
<Automatic>
<Automatic>
PTE3_InitValue
false
false
<Automatic>
<Automatic>
PTE3_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD7
false
false
true
PTD7_UserName
false
false
PTD7
PTD7_ISF
false
false
<Automatic>
<Automatic>
PTD7_IRQC
false
false
<Automatic>
<Automatic>
PTD7_MUX
false
false
<Automatic>
<Automatic>
PTD7_LK
false
false
<Automatic>
<Automatic>
PTD7_PE
false
false
<Automatic>
<Automatic>
PTD7_PS
false
false
<Automatic>
<Automatic>
PTD7_InitValue
false
false
<Automatic>
<Automatic>
PTD7_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD6
false
false
true
PTD6_UserName
false
false
PTD6
PTD6_ISF
false
false
<Automatic>
<Automatic>
PTD6_IRQC
false
false
<Automatic>
<Automatic>
PTD6_MUX
false
false
<Automatic>
<Automatic>
PTD6_LK
false
false
<Automatic>
<Automatic>
PTD6_PE
false
false
<Automatic>
<Automatic>
PTD6_PS
false
false
<Automatic>
<Automatic>
PTD6_InitValue
false
false
<Automatic>
<Automatic>
PTD6_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC0
false
false
true
PTC0_UserName
false
false
PTC0
PTC0_ISF
false
false
<Automatic>
<Automatic>
PTC0_IRQC
false
false
<Automatic>
<Automatic>
PTC0_MUX
false
false
<Automatic>
<Automatic>
PTC0_LK
false
false
<Automatic>
<Automatic>
PTC0_PE
false
false
<Automatic>
<Automatic>
PTC0_PS
false
false
<Automatic>
<Automatic>
PTC0_InitValue
false
false
<Automatic>
<Automatic>
PTC0_DigitalFilter
false
false
<Automatic>
<Automatic>
PTC17
false
false
true
PTC17_UserName
false
false
PTC17
PTC17_ISF
false
false
<Automatic>
<Automatic>
PTC17_IRQC
false
false
<Automatic>
<Automatic>
PTC17_MUX
false
false
<Automatic>
<Automatic>
PTC17_LK
false
false
<Automatic>
<Automatic>
PTC17_PE
false
false
<Automatic>
<Automatic>
PTC17_PS
false
false
<Automatic>
<Automatic>
PTC17_InitValue
false
false
<Automatic>
<Automatic>
PTC17_DigitalFilter
false
false
<Automatic>
<Automatic>
PTA6
false
false
true
PTA6_UserName
false
false
PTA6
PTA6_ISF
false
false
<Automatic>
<Automatic>
PTA6_IRQC
false
false
<Automatic>
<Automatic>
PTA6_MUX
false
false
<Automatic>
<Automatic>
PTA6_LK
false
false
<Automatic>
<Automatic>
PTA6_PE
false
false
<Automatic>
<Automatic>
PTA6_PS
false
false
<Automatic>
<Automatic>
PTA6_InitValue
false
false
<Automatic>
<Automatic>
PTA6_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE7
false
false
true
PTE7_UserName
false
false
PTE7
PTE7_ISF
false
false
<Automatic>
<Automatic>
PTE7_IRQC
false
false
<Automatic>
<Automatic>
PTE7_MUX
false
false
<Automatic>
<Automatic>
PTE7_LK
false
false
<Automatic>
<Automatic>
PTE7_PE
false
false
<Automatic>
<Automatic>
PTE7_PS
false
false
<Automatic>
<Automatic>
PTE7_InitValue
false
false
<Automatic>
<Automatic>
PTE7_DigitalFilter
false
false
<Automatic>
<Automatic>
PTB12
false
false
true
PTB12_UserName
false
false
PTB12
PTB12_ISF
false
false
<Automatic>
<Automatic>
PTB12_IRQC
false
false
<Automatic>
<Automatic>
PTB12_MUX
false
false
<Automatic>
<Automatic>
PTB12_LK
false
false
<Automatic>
<Automatic>
PTB12_PE
false
false
<Automatic>
<Automatic>
PTB12_PS
false
false
<Automatic>
<Automatic>
PTB12_InitValue
false
false
<Automatic>
<Automatic>
PTB12_DigitalFilter
false
false
<Automatic>
<Automatic>
PTD4
false
false
true
PTD4_UserName
false
false
PTD4
PTD4_ISF
false
false
<Automatic>
<Automatic>
PTD4_IRQC
false
false
<Automatic>
<Automatic>
PTD4_MUX
false
false
<Automatic>
<Automatic>
PTD4_LK
false
false
<Automatic>
<Automatic>
PTD4_PE
false
false
<Automatic>
<Automatic>
PTD4_PS
false
false
<Automatic>
<Automatic>
PTD4_InitValue
false
false
<Automatic>
<Automatic>
PTD4_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE6
false
false
true
PTE6_UserName
false
false
PTE6
PTE6_ISF
false
false
<Automatic>
<Automatic>
PTE6_IRQC
false
false
<Automatic>
<Automatic>
PTE6_MUX
false
false
<Automatic>
<Automatic>
PTE6_LK
false
false
<Automatic>
<Automatic>
PTE6_PE
false
false
<Automatic>
<Automatic>
PTE6_PS
false
false
<Automatic>
<Automatic>
PTE6_InitValue
false
false
<Automatic>
<Automatic>
PTE6_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE2
false
false
true
PTE2_UserName
false
false
PTE2
PTE2_ISF
false
false
<Automatic>
<Automatic>
PTE2_IRQC
false
false
<Automatic>
<Automatic>
PTE2_MUX
false
false
<Automatic>
<Automatic>
PTE2_LK
false
false
<Automatic>
<Automatic>
PTE2_PE
false
false
<Automatic>
<Automatic>
PTE2_PS
false
false
<Automatic>
<Automatic>
PTE2_InitValue
false
false
<Automatic>
<Automatic>
PTE2_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE1
false
false
true
PTE1_UserName
false
false
PTE1
PTE1_ISF
false
false
<Automatic>
<Automatic>
PTE1_IRQC
false
false
<Automatic>
<Automatic>
PTE1_MUX
false
false
<Automatic>
<Automatic>
PTE1_LK
false
false
<Automatic>
<Automatic>
PTE1_DSE
false
false
<Automatic>
<Automatic>
PTE1_PE
false
false
<Automatic>
<Automatic>
PTE1_PS
false
false
<Automatic>
<Automatic>
PTE1_InitValue
false
false
<Automatic>
<Automatic>
PTE1_DigitalFilter
false
false
<Automatic>
<Automatic>
PTE0
false
false
true
PTE0_UserName
false
false
PTE0
PTE0_ISF
false
false
<Automatic>
<Automatic>
PTE0_IRQC
false
false
<Automatic>
<Automatic>
PTE0_MUX
false
false
<Automatic>
<Automatic>
PTE0_LK
false
false
<Automatic>
<Automatic>
PTE0_DSE
false
false
<Automatic>
<Automatic>
PTE0_PE
false
false
<Automatic>
<Automatic>
PTE0_PS
false
false
<Automatic>
<Automatic>
PTE0_InitValue
false
false
<Automatic>
<Automatic>
PTE0_DigitalFilter
false
false
<Automatic>
<Automatic>
ProcessorSpecificMethods
1
Beans\PinSettings\MethodsS32K118_48.item
PeripheralTypeMethodsInvisibleGroup
false
false
PINS_DRV_Init
false
0
true
true
always
PINS_DRV_Init
PINS_DRV_SetPullSel
false
0
true
true
always
PINS_DRV_SetPullSel
PINS_DRV_SetMuxModeSel
false
0
true
true
always
PINS_DRV_SetMuxModeSel
PINS_DRV_SetPinIntSel
false
0
true
true
always
PINS_DRV_SetPinIntSel
PINS_DRV_GetPinIntSel
false
0
true
true
always
PINS_DRV_GetPinIntSel
PINS_DRV_ClearPinIntFlagCmd
false
0
true
true
always
PINS_DRV_ClearPinIntFlagCmd
PINS_DRV_EnableDigitalFilter
false
0
true
true
always
PINS_DRV_EnableDigitalFilter
PINS_DRV_DisableDigitalFilter
false
0
true
true
always
PINS_DRV_DisableDigitalFilter
PINS_DRV_ConfigDigitalFilter
false
0
true
true
always
PINS_DRV_ConfigDigitalFilter
PINS_DRV_GetPortIntFlag
false
0
true
true
always
PINS_DRV_GetPortIntFlag
PINS_DRV_ClearPortIntFlagCmd
false
0
true
true
always
PINS_DRV_ClearPortIntFlagCmd
PINS_DRV_SetGlobalPinControl
false
0
true
true
always
PINS_DRV_SetGlobalPinControl
PINS_DRV_SetGlobalIntControl
false
0
true
true
always
PINS_DRV_SetGlobalIntControl
PINS_DRV_GetPinsDirection
false
0
true
true
always
PINS_DRV_GetPinsDirection
PINS_DRV_SetPinDirection
false
0
true
true
always
PINS_DRV_SetPinDirection
PINS_DRV_SetPinsDirection
false
0
true
true
always
PINS_DRV_SetPinsDirection
PINS_DRV_WritePin
false
0
true
true
always
PINS_DRV_WritePin
PINS_DRV_WritePins
false
0
true
true
always
PINS_DRV_WritePins
PINS_DRV_GetPinsOutput
false
0
true
true
always
PINS_DRV_GetPinsOutput
PINS_DRV_SetPins
false
0
true
true
always
PINS_DRV_SetPins
PINS_DRV_ClearPins
false
0
true
true
always
PINS_DRV_ClearPins
PINS_DRV_TogglePins
false
0
true
true
always
PINS_DRV_TogglePins
PINS_DRV_ReadPins
false
0
true
true
always
PINS_DRV_ReadPins
file:/${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0/tools/pex/Repositories/SDK_S32K1xx_15_Repository
com.freescale.processorexpert.ksdk.clock_manager
clock_manager
clockMan1
3
true
ALWAYS_WRITE
CLOCKS_LDD
SDK_S32K1xx_15
false
DeviceName
false
false
clockMan1
CompVersion
S32_SDK_S32K
Settings
false
false
ClocksSettings
1
CPUs\S32K118_48\CPU_ClockSettings.item
ClockManagement
false
false
true
clock_managerCfg
false
1
false
true
CPUs\S32K118_64\CPU_ClockSettingsItem.item
clock_managerCfg_0
false
false
true
ClockSettingsGrp0
false
false
false
PeripheralClocksCount0
false
false
10
PeripheralClocksGrp0
false
false
false
Peripheral17_CLK_Grp0
false
false
true
Peripheral17_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral17_CLkEnable0
false
false
false
false
false
Peripheral17_CLOCK_NAME0
ADC0_CLK
Peripheral17_MODULE_NAME0
ADC
Peripheral17_INTF_CLK0
BUS_CLK
Peripheral17_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral17_MUL_SEL0
Peripheral17_DIV_SEL0
Peripheral17_FUNC_CLK0
0 Hz
Peripheral31_CLK_Grp0
false
false
true
Peripheral31_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral31_CLkEnable0
false
false
false
false
false
Peripheral31_CLOCK_NAME0
CMP0_CLK
Peripheral31_MODULE_NAME0
CMP
Peripheral31_INTF_CLK0
BUS_CLK
Peripheral31_FUNC_SEL0
Peripheral31_MUL_SEL0
Peripheral31_DIV_SEL0
Peripheral31_FUNC_CLK0
0 Hz
Peripheral11_CLK_Grp0
false
false
true
Peripheral11_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral11_CLkEnable0
false
false
false
false
false
Peripheral11_CLOCK_NAME0
CRC0_CLK
Peripheral11_MODULE_NAME0
CRC
Peripheral11_INTF_CLK0
BUS_CLK
Peripheral11_FUNC_SEL0
Peripheral11_MUL_SEL0
Peripheral11_DIV_SEL0
Peripheral11_FUNC_CLK0
0 Hz
Peripheral1_CLK_Grp0
false
false
true
Peripheral1_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral1_CLkEnable0
false
false
false
true
true
Peripheral1_CLOCK_NAME0
DMAMUX0_CLK
Peripheral1_MODULE_NAME0
DMA
Peripheral1_INTF_CLK0
BUS_CLK
Peripheral1_FUNC_SEL0
Peripheral1_MUL_SEL0
Peripheral1_DIV_SEL0
Peripheral1_FUNC_CLK0
0 Hz
Peripheral2_CLK_Grp0
false
false
true
Peripheral2_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral2_CLkEnable0
false
false
false
false
false
Peripheral2_CLOCK_NAME0
FlexCAN0_CLK
Peripheral2_MODULE_NAME0
CAN
Peripheral2_INTF_CLK0
SYS_CLK
Peripheral2_FUNC_SEL0
Peripheral2_MUL_SEL0
Peripheral2_DIV_SEL0
Peripheral2_FUNC_CLK0
0 Hz
Peripheral25_CLK_Grp0
false
false
true
Peripheral25_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral25_CLkEnable0
false
false
false
true
true
Peripheral25_CLOCK_NAME0
FLEXIO0_CLK
Peripheral25_MODULE_NAME0
FLEXIO
Peripheral25_INTF_CLK0
BUS_CLK
Peripheral25_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral25_MUL_SEL0
Peripheral25_DIV_SEL0
Peripheral25_FUNC_CLK0
8 MHz
Peripheral0_CLK_Grp0
false
false
true
Peripheral0_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral0_CLkEnable0
false
false
false
false
false
Peripheral0_CLOCK_NAME0
FTFC0_CLK
Peripheral0_MODULE_NAME0
FTFC
Peripheral0_INTF_CLK0
SLOW_CLK
Peripheral0_FUNC_SEL0
Peripheral0_MUL_SEL0
Peripheral0_DIV_SEL0
Peripheral0_FUNC_CLK0
0 Hz
Peripheral14_CLK_Grp0
false
false
true
Peripheral14_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral14_CLkEnable0
false
false
false
false
false
Peripheral14_CLOCK_NAME0
FTM0_CLK
Peripheral14_MODULE_NAME0
FTM
Peripheral14_INTF_CLK0
SYS_CLK
Peripheral14_FUNC_SEL0
false
false
false
typePCS_DIV1_CLK2
2
CLK_SRC_SIRC_DIV1
Peripheral14_MUL_SEL0
Peripheral14_DIV_SEL0
Peripheral14_FUNC_CLK0
0 Hz
Peripheral15_CLK_Grp0
false
false
true
Peripheral15_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral15_CLkEnable0
false
false
false
false
false
Peripheral15_CLOCK_NAME0
FTM1_CLK
Peripheral15_MODULE_NAME0
FTM
Peripheral15_INTF_CLK0
SYS_CLK
Peripheral15_FUNC_SEL0
false
false
false
typePCS_DIV1_CLK2
2
CLK_SRC_SIRC_DIV1
Peripheral15_MUL_SEL0
Peripheral15_DIV_SEL0
Peripheral15_FUNC_CLK0
0 Hz
Peripheral27_CLK_Grp0
false
false
true
Peripheral27_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral27_CLkEnable0
false
false
false
true
true
Peripheral27_CLOCK_NAME0
LPI2C0_CLK
Peripheral27_MODULE_NAME0
I2C
Peripheral27_INTF_CLK0
BUS_CLK
Peripheral27_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral27_MUL_SEL0
Peripheral27_DIV_SEL0
Peripheral27_FUNC_CLK0
8 MHz
Peripheral13_CLK_Grp0
false
false
true
Peripheral13_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral13_CLkEnable0
false
false
false
false
false
Peripheral13_CLOCK_NAME0
LPIT0_CLK
Peripheral13_MODULE_NAME0
LPIT
Peripheral13_INTF_CLK0
BUS_CLK
Peripheral13_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral13_MUL_SEL0
Peripheral13_DIV_SEL0
Peripheral13_FUNC_CLK0
0 Hz
Peripheral7_CLK_Grp0
false
false
true
Peripheral7_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral7_CLkEnable0
false
false
false
false
false
Peripheral7_CLOCK_NAME0
LPSPI0_CLK
Peripheral7_MODULE_NAME0
SPI
Peripheral7_INTF_CLK0
BUS_CLK
Peripheral7_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral7_MUL_SEL0
Peripheral7_DIV_SEL0
Peripheral7_FUNC_CLK0
0 Hz
Peripheral8_CLK_Grp0
false
false
true
Peripheral8_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral8_CLkEnable0
false
false
false
false
false
Peripheral8_CLOCK_NAME0
LPSPI1_CLK
Peripheral8_MODULE_NAME0
SPI
Peripheral8_INTF_CLK0
BUS_CLK
Peripheral8_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral8_MUL_SEL0
Peripheral8_DIV_SEL0
Peripheral8_FUNC_CLK0
0 Hz
Peripheral19_CLK_Grp0
false
false
true
Peripheral19_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral19_CLkEnable0
false
false
false
false
false
Peripheral19_CLOCK_NAME0
LPTMR0_CLK
Peripheral19_MODULE_NAME0
LPTMR
Peripheral19_INTF_CLK0
BUS_CLK
Peripheral19_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral19_MUL_SEL0
false
false
false
typePCC_FRAC
0
MULTIPLY_BY_ONE
Peripheral19_DIV_SEL0
false
false
false
typePCC_DIV
0
DIVIDE_BY_ONE
Peripheral19_FUNC_CLK0
0 Hz
Peripheral28_CLK_Grp0
false
false
true
Peripheral28_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral28_CLkEnable0
false
false
false
true
true
Peripheral28_CLOCK_NAME0
LPUART0_CLK
Peripheral28_MODULE_NAME0
LPUART
Peripheral28_INTF_CLK0
BUS_CLK
Peripheral28_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral28_MUL_SEL0
Peripheral28_DIV_SEL0
Peripheral28_FUNC_CLK0
8 MHz
Peripheral29_CLK_Grp0
false
false
true
Peripheral29_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral29_CLkEnable0
false
false
false
true
true
Peripheral29_CLOCK_NAME0
LPUART1_CLK
Peripheral29_MODULE_NAME0
LPUART
Peripheral29_INTF_CLK0
BUS_CLK
Peripheral29_FUNC_SEL0
false
false
false
typePCS_DIV2_CLK2
2
CLK_SRC_SIRC_DIV2
Peripheral29_MUL_SEL0
Peripheral29_DIV_SEL0
Peripheral29_FUNC_CLK0
8 MHz
Peripheral12_CLK_Grp0
false
false
true
Peripheral12_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral12_CLkEnable0
false
false
false
false
false
Peripheral12_CLOCK_NAME0
PDB0_CLK
Peripheral12_MODULE_NAME0
PDB
Peripheral12_INTF_CLK0
SYS_CLK
Peripheral12_FUNC_SEL0
Peripheral12_MUL_SEL0
Peripheral12_DIV_SEL0
Peripheral12_FUNC_CLK0
0 Hz
Peripheral20_CLK_Grp0
false
false
true
Peripheral20_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral20_CLkEnable0
false
false
false
true
true
Peripheral20_CLOCK_NAME0
PORTA_CLK
Peripheral20_MODULE_NAME0
PinSettings
Peripheral20_INTF_CLK0
BUS_CLK
Peripheral20_FUNC_SEL0
Peripheral20_MUL_SEL0
Peripheral20_DIV_SEL0
Peripheral20_FUNC_CLK0
0 Hz
Peripheral21_CLK_Grp0
false
false
true
Peripheral21_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral21_CLkEnable0
false
false
false
true
true
Peripheral21_CLOCK_NAME0
PORTB_CLK
Peripheral21_MODULE_NAME0
PinSettings
Peripheral21_INTF_CLK0
BUS_CLK
Peripheral21_FUNC_SEL0
Peripheral21_MUL_SEL0
Peripheral21_DIV_SEL0
Peripheral21_FUNC_CLK0
0 Hz
Peripheral22_CLK_Grp0
false
false
true
Peripheral22_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral22_CLkEnable0
false
false
false
true
true
Peripheral22_CLOCK_NAME0
PORTC_CLK
Peripheral22_MODULE_NAME0
PinSettings
Peripheral22_INTF_CLK0
BUS_CLK
Peripheral22_FUNC_SEL0
Peripheral22_MUL_SEL0
Peripheral22_DIV_SEL0
Peripheral22_FUNC_CLK0
0 Hz
Peripheral23_CLK_Grp0
false
false
true
Peripheral23_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral23_CLkEnable0
false
false
false
true
true
Peripheral23_CLOCK_NAME0
PORTD_CLK
Peripheral23_MODULE_NAME0
PinSettings
Peripheral23_INTF_CLK0
BUS_CLK
Peripheral23_FUNC_SEL0
Peripheral23_MUL_SEL0
Peripheral23_DIV_SEL0
Peripheral23_FUNC_CLK0
0 Hz
Peripheral24_CLK_Grp0
false
false
true
Peripheral24_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
1
Disabled
Peripheral24_CLkEnable0
false
false
false
true
true
Peripheral24_CLOCK_NAME0
PORTE_CLK
Peripheral24_MODULE_NAME0
PinSettings
Peripheral24_INTF_CLK0
BUS_CLK
Peripheral24_FUNC_SEL0
Peripheral24_MUL_SEL0
Peripheral24_DIV_SEL0
Peripheral24_FUNC_CLK0
0 Hz
Peripheral18_CLK_Grp0
false
false
true
Peripheral18_SetModuleClockGateAutomatically0
false
false
false
typeClockEnaDis
0
Enabled
Peripheral18_CLkEnable0
false
false
false
false
false
Peripheral18_CLOCK_NAME0
RTC0_CLK
Peripheral18_MODULE_NAME0
RTC
Peripheral18_INTF_CLK0
BUS_CLK
Peripheral18_FUNC_SEL0
Peripheral18_MUL_SEL0
Peripheral18_DIV_SEL0
Peripheral18_FUNC_CLK0
0 Hz
FunctionalClocksGrp0
false
false
false
RUN_Grp0
false
false
true
SIRC_DIVIDER10
false
false
false
typeASYNC_SIRC_DIV
0
SCG_ASYNC_CLOCK_DIV_BY_1
FIRC_DIVIDER10
false
false
false
typeASYNC_FIRC_DIV
0
SCG_ASYNC_CLOCK_DIV_BY_1
SOSC_DIVIDER10
false
false
false
typeASYNC_SOSC_DIV
0
SCG_ASYNC_CLOCK_DIV_BY_1
SIRC_DIVIDER20
false
false
false
typeASYNC_SIRC_DIV
0
SCG_ASYNC_CLOCK_DIV_BY_1
FIRC_DIVIDER20
false
false
false
typeASYNC_FIRC_DIV
0
SCG_ASYNC_CLOCK_DIV_BY_1
SOSC_DIVIDER20
false
false
false
typeASYNC_SOSC_DIV
0
SCG_ASYNC_CLOCK_DIV_BY_1
Freq_Grp0
false
false
true
SIRCDIV1_CLK0
8 MHz
FIRCDIV1_CLK0
48 MHz
SOSCDIV1_CLK0
0 Hz
SIRCDIV2_CLK0
8 MHz
FIRCDIV2_CLK0
48 MHz
SOSCDIV2_CLK0
0 Hz
InterfaceClocksGrp0
false
false
false
SCS_CLK_Grp0
false
false
true
RUN_SCS0
false
false
false
typeRCCR__SCS
2
SCG_SYSTEM_CLOCK_SRC_FIRC
RUN_SCS_CLK0
48 MHz
VLPR_SCS0
false
false
false
typeVCCR__SCS
0
SCG_SYSTEM_CLOCK_SRC_SIRC
VLPR_SCS_CLK0
8 MHz
SCS_CLKDescription0
System clock source
SYS_CLK_Grp0
false
false
true
RUN_DIVCORE0
false
false
false
typexCCR_FIRC_DIV_1_16_0
0
SCG_SYSTEM_CLOCK_DIV_BY_1
RUN_DIVCORE_CLK0
48 MHz
VLPR_DIVCORE0
false
false
false
typexCCR_SIRC_DIV_1_16_0
1
SCG_SYSTEM_CLOCK_DIV_BY_2
VLPR_DIVCORE_CLK0
4 MHz
SYS_CLKDescription0
Core clock
BUS_CLK_Grp0
false
false
true
RUN_DIVBUS0
false
false
false
typexCCR_FIRC_DIV_1_16_0
1
SCG_SYSTEM_CLOCK_DIV_BY_2
RUN_DIVBUS_CLK0
24 MHz
VLPR_DIVBUS0
false
false
false
typexCCR_SIRC_DIV_1_16_1
0
SCG_SYSTEM_CLOCK_DIV_BY_1
VLPR_DIVBUS_CLK0
4 MHz
BUS_CLKDescription0
Bus clock
SLOW_CLK_Grp0
false
false
true
RUN_DIVSLOW0
false
false
false
typexCCR_FIRC_DIV_1_8_0
1
SCG_SYSTEM_CLOCK_DIV_BY_2
RUN_DIVSLOW_CLK0
24 MHz
VLPR_DIVSLOW0
false
false
false
typexCCR_SIRC_DIV_1_8_1
3
SCG_SYSTEM_CLOCK_DIV_BY_4
VLPR_DIVSLOW_CLK0
1 MHz
SLOW_CLKDescription0
Flash clock
ClockSourcesGrp0
false
false
false
SIRC_CLK_Grp0
false
false
true
SIRC_CLKEnable0
false
false
false
true
true
SIRCReference0
SIRCPrediv0
SIRCMult0
SIRCFrequency0
false
false
false
typeSIRC_RANGE
0
SCG_SIRC_RANGE_HIGH
SIRCMonitor0
SIRCDescription0
Slow internal reference clock
FIRC_CLK_Grp0
false
false
true
FIRC_CLKEnable0
false
false
false
true
true
FIRCReference0
FIRCPrediv0
FIRCMult0
FIRCFrequency0
false
false
false
typeFIRC_RANGE
0
SCG_FIRC_RANGE_48M
FIRCMonitor0
FIRCDescription0
Fast internal reference clock
SOSC_CLK_Grp0
false
false
true
SOSC_CLKEnable0
false
false
false
false
false
SOSCReference0
false
false
false
typeSOSC_REF
1
SCG_SOSC_REF_OSC
SOSCPrediv0
SOSCMult0
SOSCFrequency0
false
false
16000000
SOSCMonitor0
false
false
false
typeCLK_MONITOR
0
SCG_MONITOR_DISABLE
SOSCDescription0
System oscillator clock
LPO_CLK_Grp0
false
false
true
LPO_CLKEnable0
false
false
false
true
true
LPOReference0
LPOPrediv0
LPOMult0
LPOFrequency0
false
false
false
typeLPO_RANGE
0
LPO_RANGE_128kHz
LPOMonitor0
LPODescription0
Low Power Oscillator
SIRCGrp0
false
false
true
Init_SIRCGrp0
false
false
true
SIRC_CLKEnableDetail0
false
false
false
typeClockEnaDis
0
Enabled
SIRCCSRGrp0
false
false
true
SIRCCSR_SIRCEN0
false
false
false
typeSIRCCSR_SIRCEN
1
state_1
SIRCCSR_SIRCSTEN0
false
false
false
typeSIRCCSR_SIRCSTEN
0
false
SIRCCSR_SIRCLPEN0
false
false
false
typeSIRCCSR_SIRCLPEN
1
true
SIRCCSR_LK0
false
false
false
typeSIRCCSR_LK
0
false
SIRCCFGGrp0
false
false
true
SIRCCFG_RANGE0
false
false
false
typeSIRCCFG_RANGE
0
SCG_SIRC_RANGE_HIGH
FIRCGrp0
false
false
true
Init_FIRCGrp0
false
false
true
FIRC_CLKEnableDetail0
false
false
false
typeClockEnaDis
0
Enabled
FIRCdefaultWarningLabel0
Warning: FIRC is default system clock!
FIRCCSRGrp0
false
false
true
FIRCCSR_FIRCEN0
false
false
false
typeFIRCCSR_FIRCEN
1
state_1
FIRCCSR_FIRCREGOFF0
false
false
false
typeFIRCCSR_FIRCREGOFF
0
true
FIRCCSR_LK0
false
false
false
typeFIRCCSR_LK
0
false
FIRCCFGGrp0
false
false
true
FIRCCFG_RANGE0
false
typeFIRCCFG_RANGE
0
SCG_FIRC_RANGE_48M
FIRCCSR_FIRCTRENGrp0
false
false
false
false
false
FIRCCSR_FIRCTRUP0
false
false
false
typeFIRCCSR_FIRCTRUP
0
false
FIRCSTATEnableGrp0
false
false
false
false
false
FIRCSTATGrp0
false
false
true
FIRCSTAT_TRIMCOAR0
false
false
false
0
DEC
FIRCSTAT_TRIMFINE0
false
false
false
0
DEC
FIRCCSR_FIRCERR0
false
false
false
typeFIRCCSR_FIRCERR
0
state_0
RTCGrp0
false
false
true
Init_RTCGrp0
false
false
false
true
true
RTC_CLKINClockUserValue0
false
false
false
0
DEC
LPOCLKS_RTCCLKSEL0
false
false
false
typeLPOCLKS_RTCCLKSEL
0
SIM_RTCCLK_SEL_SOSCDIV1_CLK
SOSCGrp0
false
false
true
Init_SOSCGrp0
false
false
true
SOSC_CLKEnableDetail0
false
false
false
typeClockEnaDis
1
Disabled
SOSCCSRGrp0
false
false
true
SOSCCSR_SOSCEN0
false
false
false
typeSOSCCSR_SOSCEN
0
state_0
SOSCCSR_SOSCERCLKEN0
false
false
false
typeSOSCCSR_SOSCERCLKEN
0
false
SOSCCSR_SOSCCM0
false
false
false
typeSOSCCSR_SOSCCM
0
SCG_SOSC_MONITOR_DISABLE
SOSCCSR_SOSCCMRE0
false
false
false
typeSOSCCSR_SOSCCMRE
0
state_0
SOSCCSR_LK0
false
false
false
typeSOSCCSR_LK
0
false
SOSCCSR_SOSCVLD0
false
false
false
typeSOSCCSR_SOSCVLD
0
state_0
SOSCCSR_SOSCSEL0
false
false
false
typeSOSCCSR_SOSCSEL
0
state_0
SOSCCSR_SOSCERR0
false
false
false
typeSOSCCSR_SOSCERR
0
state_0
SOSCCFGGrp0
false
false
true
SOSCClockUserValue0
false
false
false
16000000
DEC
SOSCCFG_EREFS0
false
false
false
typeSOSCCFG_EREFS
1
SCG_SOSC_REF_OSC
SOSCCFG_HGO0
false
false
false
typeSOSCCFG_HGO
0
SCG_SOSC_GAIN_LOW
SOSCCFG_RANGE0
false
false
false
typeSOSCCFG_RANGE
1
SCG_SOSC_RANGE_HIGH
SOSCCFG_SC2P0
false
false
false
typeSOSCCFG_SC2P
0
state_0
SOSCCFG_SC4P0
false
false
false
typeSOSCCFG_SC4P
0
state_0
SOSCCFG_SC8P0
false
false
false
typeSOSCCFG_SC8P
0
state_0
SOSCCFG_SC16P0
false
false
false
typeSOSCCFG_SC16P
0
state_0
CLKOUTGrp0
false
false
true
Init_CLKOUTGrp0
false
false
false
true
true
CHIPCTL_ADC_INTERLEAVE_EN0
false
false
false
typeCHIPCTL_ADC_INTERLEAVE_EN
0
state_0000
CHIPCTL_CLKOUTEN0
false
false
false
typeCHIPCTL_CLKOUTEN
0
false
CHIPCTL_CLKOUTSEL0
false
false
false
typeCHIPCTL_CLKOUTSEL
0
SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT
CHIPCTL_CLKOUTDIV0
false
false
false
typeCHIPCTL_CLKOUTDIV
0
SIM_CLKOUT_DIV_BY_1
CLKOUTCNFG_CLKOUTSEL0
false
false
false
typeCLKOUTCNFG_CLKOUTSEL
3
SCG_CLOCKOUT_SRC_FIRC
CHIPCTL_PDB_BB_SEL0
false
false
false
typeCHIPCTL_PDB_BB_SEL
0
state_0
CHIPCTL_COCO_TRG_SEL0
false
false
false
typeCHIPCTL_COCO_TRG_SEL
0
state_0
FTMOPT0Grp0
false
false
true
FTMOPT0_FTM0FLTxSEL0
false
false
false
0
DEC
FTMOPT0_FTM1FLTxSEL0
false
false
false
0
DEC
FTMOPT0_FTM2FLTxSEL0
false
false
false
0
DEC
FTMOPT0_FTM3FLTxSEL0
false
false
false
0
DEC
FTMOPT0_FTM0CLKSEL0
false
false
false
typeFTMOPT0_FTM0CLKSEL
0
state_00
FTMOPT0_FTM1CLKSEL0
false
false
false
typeFTMOPT0_FTM1CLKSEL
0
state_00
FTMOPT0_FTM2CLKSEL0
false
false
false
typeFTMOPT0_FTM2CLKSEL
0
state_00
FTMOPT0_FTM3CLKSEL0
false
false
false
typeFTMOPT0_FTM3CLKSEL
0
state_00
LPOGrp0
false
false
true
Init_LPOGrp0
false
false
false
true
true
REGSC_LPOEN0
false
false
false
typeREGSC_LPOEN
1
true
WriteOnceWarningLabel0
Warning: Write once register (LPOCLKS)!
LPOCLKS_LPO1KCLKEN0
false
false
false
typeLPOCLKS_LPO1KCLKEN
1
true
LPOCLKS_LPO32KCLKEN0
false
false
false
typeLPOCLKS_LPO32KCLKEN
1
true
LPOCLKS_LPOCLKSEL0
false
false
false
typeLPOCLKS_LPOCLKSEL
0
SIM_LPO_CLK_SEL_LPO_128K
Manual_trimm_LPO0
false
false
0
true
LPOTRIM_LPOTRIM0
false
false
false
typeLPOTRIM_LPOTRIM
16
0
ADCOPTGrp0
false
false
true
ADCOPT_ADC0TRGSEL0
false
false
false
typeADCOPT_ADC0TRGSEL
0
state_0
ADCOPT_ADC0SWPRETRG0
false
false
false
typeADCOPT_ADC0SWPRETRG
0
state_000
ADCOPT_ADC0PRETRGSEL0
false
false
false
typeADCOPT_ADC0PRETRGSEL
0
state_00
ADCOPT_ADC1TRGSEL0
false
false
false
typeADCOPT_ADC1TRGSEL
0
state_0
ADCOPT_ADC1SWPRETRG0
false
false
false
typeADCOPT_ADC1SWPRETRG
0
state_000
ADCOPT_ADC1PRETRGSEL0
false
false
false
typeADCOPT_ADC1PRETRGSEL
0
state_00
FTMOPT1Grp0
false
false
true
FTMOPT1_FTM0SYNCBIT0
false
false
false
typeFTMOPT1_FTM0SYNCBIT
0
state_0
FTMOPT1_FTM1SYNCBIT0
false
false
false
typeFTMOPT1_FTM1SYNCBIT
0
state_0
FTMOPT1_FTM2SYNCBIT0
false
false
false
typeFTMOPT1_FTM2SYNCBIT
0
state_0
FTMOPT1_FTM3SYNCBIT0
false
false
false
typeFTMOPT1_FTM3SYNCBIT
0
state_0
FTMOPT1_FTM1CH0SEL0
false
false
false
typeFTMOPT1_FTM1CH0SEL
0
state_00
FTMOPT1_FTM2CH0SEL0
false
false
false
typeFTMOPT1_FTM2CH0SEL
0
state_00
FTMOPT1_FTM2CH1SEL0
false
false
false
typeFTMOPT1_FTM2CH1SEL
0
state_0
FTMOPT1_FTM0_OUTSEL0
false
false
false
typeFTMOPT1_FTM0_OUTSEL
0
state_0
FTMOPT1_FTM3_OUTSEL0
false
false
false
typeFTMOPT1_FTM3_OUTSEL
0
state_0
SDIDGrp0
false
false
true
SIMGrp0
false
false
true
Init_SIMGrp0
false
false
false
true
true
PLATCGC_CGCMSCM0
false
false
false
typePLATCGC_CGCMSCM
1
true
PLATCGC_CGCMPU0
false
false
false
typePLATCGC_CGCMPU
1
true
PLATCGC_CGCDMA0
false
false
false
typePLATCGC_CGCDMA
1
true
PLATCGC_CGCERM0
false
false
false
typePLATCGC_CGCERM
1
true
PLATCGC_CGCEIM0
false
false
false
typePLATCGC_CGCEIM
1
true
TCLKGrp0
false
false
true
Init_TCLKGrp0
false
false
false
true
true
TClock0UserValue0
false
false
false
0
DEC
TClock1UserValue0
false
false
false
0
DEC
TClock2UserValue0
false
false
false
0
DEC
FCFG1Grp0
false
false
true
FCFG1_FLASHDIS0
false
false
false
typeFCFG1_FLASHDIS
0
state_0
FCFG1_FLASHDOZE0
false
false
false
typeFCFG1_FLASHDOZE
0
state_0
FCFG1_DEPART0
false
false
false
0
DEC
FCFG1_EEERAMSIZE0
false
false
false
typeFCFG1_EEERAMSIZE
0
state_0000
FCFG1_PFSIZE0
false
false
false
typeFCFG1_PFSIZE
0
state_0000
FCFG1_NVMSIZE0
false
false
false
typeFCFG1_NVMSIZE
0
state_0000
FCFG2Grp0
false
false
true
FCFG2_MAXADDR10
false
false
false
127
DEC
FCFG2_MAXADDR00
false
false
false
127
DEC
UIDHGrp0
false
false
true
UIDH_UID127_960
false
false
false
0
DEC
UIDMHGrp0
false
false
true
UIDMH_UID95_640
false
false
false
0
DEC
UIDMLGrp0
false
false
true
UIDML_UID63_320
false
false
false
0
DEC
UIDLGrp0
false
false
true
UIDL_UID31_00
false
false
false
0
DEC
TraceGrp0
false
false
true
Init_TraceGrp0
false
false
false
true
true
CLKDIV4_TRACEDIVEN0
false
false
false
true
true
CHIPCTL_TRACECLK_SEL0
false
false
false
typeCHIPCTL_TRACECLK_SEL
0
CLOCK_TRACE_SRC_CORE_CLK
CLKDIV4_TRACEDIV0
false
false
false
0
DEC
CLKDIV4_TRACEFRAC0
false
false
false
typeCLKDIV4_TRACEFRAC
0
false
MISCTRLGrp0
false
false
true
MISCTRL_SW_TRG0
false
false
false
typeMISCTRL_SW_TRG
0
state_0
ClocksValueSummaryGrp0
false
false
true
SystemClocksGrp0
false
false
false
SIRCClockValuesGrp0
false
false
false
SIRC_CLOCK0
8000000
SIRC_CLOCK_DIV1_0
8000000
SIRC_CLOCK_DIV2_0
8000000
FIRCClockValuesGrp0
false
false
false
FIRC_CLOCK0
48000000
FIRC_CLOCK_DIV1_0
48000000
FIRC_CLOCK_DIV2_0
48000000
RTCClockValuesGrp0
false
false
false
RTC_CLKIN_CLOCK0
false
0
DEC
SOSCClockValuesGrp0
false
false
false
SOSC_CLOCK0
0
SOSC_CLOCK_DIV1_0
0
SOSC_CLOCK_DIV2_0
0
SPLLClockValuesGrp0
false
false
false
SPLL_CLOCK0
0
SPLL_CLOCK_DIV1_0
0
SPLL_CLOCK_DIV2_0
0
RunModeClockValuesGrp0
false
false
false
RUN_CORE_CLOCK0
48000000
RUN_BUS_CLOCK0
24000000
RUN_SLOW_CLOCK0
24000000
VLPRModeClockValuesGrp0
false
false
false
VLPR_CORE_CLOCK0
4000000
VLPR_BUS_CLOCK0
4000000
VLPR_SLOW_CLOCK0
1000000
HSRUNModeClockValuesGrp0
false
false
false
HSRUN_CORE_CLOCK0
0
HSRUN_BUS_CLOCK0
0
HSRUN_SLOW_CLOCK0
0
CLKOUTClockValuesGrp0
false
false
false
CLKOUT_CLOCK0
0
LPOClockValuesGrp0
false
false
false
LPO_1KHz_CLOCK0
1000
LPO_32KHz_CLOCK0
32000
LPO_128KHz_CLOCK0
128000
LPO_CLOCK0
128000
RTCCLKSEL_CLOCK0
0
TCLKClockValuesGrp0
false
false
false
TCLK0_CLOCK0
0
TCLK1_CLOCK0
0
TCLK2_CLOCK0
0
TraceClockValuesGrp0
false
false
false
TRACE_CLOCK0
48000000
ADC_0_CLOCK_GATE_0
'off'
CMP_0_CLOCK_GATE_0
'off'
CRC_0_CLOCK_GATE_0
'off'
DMAMUX_0_CLOCK_GATE_0
'on'
FlexCAN_0_CLOCK_GATE_0
'off'
FLEXIO_0_CLOCK_GATE_0
'on'
FTFC_0_CLOCK_GATE_0
'off'
FTM_0_CLOCK_GATE_0
'off'
FTM_1_CLOCK_GATE_0
'off'
LPI2C_0_CLOCK_GATE_0
'on'
LPIT_0_CLOCK_GATE_0
'off'
LPSPI_0_CLOCK_GATE_0
'off'
LPSPI_1_CLOCK_GATE_0
'off'
LPTMR_0_CLOCK_GATE_0
'off'
LPUART_0_CLOCK_GATE_0
'on'
LPUART_1_CLOCK_GATE_0
'on'
PDB_0_CLOCK_GATE_0
'off'
PORT_0_CLOCK_GATE_0
'on'
PORT_1_CLOCK_GATE_0
'on'
PORT_2_CLOCK_GATE_0
'on'
PORT_3_CLOCK_GATE_0
'on'
PORT_4_CLOCK_GATE_0
'on'
RTC_0_CLOCK_GATE_0
'off'
PeripheralInterfaceClocksGrp0
false
false
false
CMP_0_CLOCK_0
off
CRC_0_CLOCK_0
off
DMAMUX_0_CLOCK_0
off
FlexCAN_0_CLOCK_0
off
FTFC_0_CLOCK_0
off
PDB_0_CLOCK_0
off
PORT_0_CLOCK_0
off
PORT_1_CLOCK_0
off
PORT_2_CLOCK_0
off
PORT_3_CLOCK_0
off
PORT_4_CLOCK_0
off
RTC_0_CLOCK_0
off
PeripheralFunctionalClocksGrp0
false
false
false
ADC0_CLK0
0
FLEXIO0_CLK0
8000000
FTM0_CLK0
0
FTM1_CLK0
0
LPI2C0_CLK0
8000000
LPIT0_CLK0
0
LPSPI0_CLK0
0
LPSPI1_CLK0
0
LPTMR0_CLK0
0
LPUART0_CLK0
8000000
LPUART1_CLK0
8000000
StaticCallbacksConfigurations
false
1
false
true
StaticCallbackCfg0
false
false
false
false
false
CallbackConfigName0
false
false
StaticCallbackName0
false
false
StaticCallbackType0
false
false
false
0
CLOCK_MANAGER_CALLBACK_BEFORE
StaticCallbackParamGrp0
false
false
false
false
false
StaticCallbackParamName0
false
false
UserParamExtDeclaration0
false
false
LinkGrp
false
false
false
Link0
false
false
intMan1
AutoLink0
false
false
false
0
true
ClockHiddenItems
false
false
PeriphDevice
false
false
false
CpuName
S32K118_48
ProjectComponentsCount
false
false
7
PeripheralMaxIdValue
false
false
120
ProjectComponentsCountChanged
false
false
2
ModuleName_ADC
false
false
0
ModuleName_CAN
false
false
0
ModuleName_CMP
false
false
0
ModuleName_CRC
false
false
0
ModuleName_CTU
false
false
0
ModuleName_DECFILT
false
false
0
ModuleName_DMA
false
false
1
ModuleName_DSPI
false
false
0
ModuleName_DTS
false
false
0
ModuleName_eMIOS
false
false
0
ModuleName_ENET
false
false
0
ModuleName_ETIMER
false
false
0
ModuleName_ETPU
false
false
0
ModuleName_EWM
false
false
0
ModuleName_FLEXIO
false
false
0
ModuleName_FLEXRAY
false
false
0
ModuleName_FTFC
false
false
0
ModuleName_FTM
false
false
0
ModuleName_I2C
false
false
1
ModuleName_IIC
false
false
0
ModuleName_LFAST
false
false
0
ModuleName_LIN
false
false
0
ModuleName_LPIT
false
false
0
ModuleName_LPTMR
false
false
0
ModuleName_LPUART
false
false
1
ModuleName_MEMU
false
false
0
ModuleName_MCB
false
false
0
ModuleName_MLB
false
false
0
ModuleName_PDB
false
false
0
ModuleName_PinSettings
false
false
1
ModuleName_PIT
false
false
0
ModuleName_PWM
false
false
0
ModuleName_QSPI
false
false
0
ModuleName_RTC
false
false
0
ModuleName_SAI
false
false
0
ModuleName_SDHC
false
false
0
ModuleName_SENT
false
false
0
ModuleName_SGEN
false
false
0
ModuleName_SIPI
false
false
0
ModuleName_SPI
false
false
0
ModuleName_USBOTG
false
false
0
ModuleName_USBSPH
false
false
0
ModuleName_WKPU
false
false
0
ModuleName_MIPI
false
false
0
ModuleName_RADAR
false
false
0
ModuleName_SPT
false
false
0
ModuleName_WGM
false
false
0
PeripheralInterfaceClocksGrp0
false
false
false
SdkSpecificMethods
1
clock_methods_group
false
false
DriverMethodsConditional
false
false
CLOCK_DRV_Init
false
0
true
true
always
CLOCK_DRV_Init
CLOCK_DRV_GetFreq
false
0
true
true
always
CLOCK_DRV_GetFreq
CLOCK_DRV_SetModuleClock
false
0
true
true
always
CLOCK_DRV_SetModuleClock
CLOCK_DRV_SetSystemClock
false
0
true
true
always
CLOCK_DRV_SetSystemClock
CLOCK_DRV_GetSystemClockSource
false
0
true
true
always
CLOCK_DRV_GetSystemClockSource
CLOCK_DRV_SetClockSource
false
0
true
true
always
CLOCK_DRV_SetClockSource
file:/${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0/tools/pex/Repositories/SDK_S32K1xx_15_Repository
com.freescale.processorexpert.ksdk.interrupt_manager
interrupt_manager
intMan1
4
true
ALWAYS_WRITE
TRIGGER
SDK_S32K1xx_15
false
DeviceName
false
false
intMan1
CompVersion
S32K144_SDK01
VersionSpecificItem
1
Settings
false
false
SdkSpecificMethods
1
Beans\interrupt_manager\Items\S32K144_SDK01\interrupt_manager_methods.item
interrupt_managergroup
false
false
INT_SYS_InstallHandler
false
0
true
true
always
INT_SYS_InstallHandler
INT_SYS_EnableIRQ
false
0
true
true
always
INT_SYS_EnableIRQ
INT_SYS_DisableIRQ
false
0
true
true
always
INT_SYS_DisableIRQ
INT_SYS_EnableIRQGlobal
false
0
true
true
always
INT_SYS_EnableIRQGlobal
INT_SYS_DisableIRQGlobal
false
0
true
true
always
INT_SYS_DisableIRQGlobal
INT_SYS_SetPriority
false
0
true
true
always
INT_SYS_SetPriority
INT_SYS_GetPriority
false
0
true
true
always
INT_SYS_GetPriority
INT_SYS_ClearPending
false
0
true
true
always
INT_SYS_ClearPending
INT_SYS_SetPending
false
0
true
true
always
INT_SYS_SetPending
INT_SYS_GetPending
false
0
true
true
always
INT_SYS_GetPending
DriverMethodsConditional_INT_SYS_GetActive
false
false
INT_SYS_GetActive
false
0
true
true
always
INT_SYS_GetActive
SdkSpecificEvents
1
eventgroup
false
false
EventModule
false
false
Events
DefaultEvent
false
false
false
false
never
DefaultEventName
intMan1_DefaultEvent
file:/${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0/tools/pex/Repositories/SDK_S32K1xx_15_Repository
com.freescale.processorexpert.ksdk.osif
osif
osif1
5
true
ALWAYS_WRITE
OS_LDD
SDK_S32K1xx_15
false
DeviceName
osif1
CompVersion
osifcommon
VersionSpecificItem
1
Settings
false
false
PropertiesItem
1
MainConfigurationsGrp
false
false
true
OSIFVARIANT
false
false
false
0
USING_OS_Baremetal
LinkItem
1
LinkGrp
false
false
true
Link0
false
false
clockMan1
Link1
false
false
intMan1
SdkSpecificMethods
1
osifgroup
false
false
OSIF_TimeDelay
false
0
true
true
always
OSIF_TimeDelay
OSIF_MutexLock
false
0
true
true
always
OSIF_MutexLock
OSIF_MutexUnlock
false
0
true
true
always
OSIF_MutexUnlock
OSIF_MutexCreate
false
0
true
true
always
OSIF_MutexCreate
OSIF_MutexDestroy
false
0
true
true
always
OSIF_MutexDestroy
OSIF_SemaWait
false
0
true
true
always
OSIF_SemaWait
OSIF_SemaPost
false
0
true
true
always
OSIF_SemaPost
OSIF_SemaCreate
false
0
true
true
always
OSIF_SemaCreate
OSIF_SemaDestroy
false
0
true
true
always
OSIF_SemaDestroy
OSIF_GetMilliseconds
false
0
true
true
always
OSIF_GetMilliseconds
file:/${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0/tools/pex/Repositories/SDK_S32K1xx_15_Repository
com.freescale.processorexpert.ksdk.i2c_pal
i2c_pal
i2c1
8
true
ALWAYS_WRITE
PHONE_LDD
SDK_S32K1xx_15
false
DeviceName
false
false
i2c1
PeriphDevice
false
false
LPI2C0
false
CompVersion
S32K144_SDK01
ComponentName
false
false
i2c_pal
VersionSpecificItem
1
Settings
false
false
i2c_pal_general_readonly
false
false
false
1
false
MasterConfiguration
1
Beans\i2c_pal\Items\S32K144_SDK01\i2c_pal_master.item
MainMasterConfigurationsGrp
false
false
0
true
i2cMasterCfg
false
1
false
true
i2cMasterCfg_0
false
false
false
true
true
i2cMasterCfg_NAME0
false
false
i2c1_MasterConfig0
lpi2cMasterCfg_READONLY0
false
false
false
1
false
Address0
false
false
false
60
DEC
is10bitAddr0
false
false
false
1
false
MasterBaudRate0
false
false
false
100000
DEC
MasterTransferType0
false
false
false
0
I2C_PAL_USING_INTERRUPTS
OperatingMode0
false
false
false
0
I2C_PAL_STANDARD_MODE
rxDMAChannelMaster0
false
false
false
0
255
txDMAChannelMaster0
true
false
false
DMAchannel_t
0
255
CallbackMaster0
false
false
NULL
CallbackParamMaster0
NULL
SlaveConfiguration
1
MainSlaveConfigurationsGrp
false
false
0
true
i2cSlaveCfg
false
1
false
true
i2cSlaveCfg_0
false
false
false
false
false
i2cSlaveCfg_NAME0
false
false
i2c1_SlaveConfig0
lpi2cSlaveCfg_READONLY0
false
false
false
0
true
SlaveAddress0
false
false
false
0
DEC
SlaveIs10bitAddr0
false
false
false
1
false
SlaveListening0
false
false
false
0
true
SlaveOperatingMode0
false
false
false
0
I2C_PAL_STANDARD_MODE
SlaveTransferType0
false
false
false
0
I2C_PAL_USING_INTERRUPTS
DMAChannelSlave0
false
false
false
DMAchannel_t
0
255
CallbackSlave0
false
false
NULL
CallbackParamSlave0
NULL
LinkItem
1
Beans\i2c_pal\Items\S32K144_SDK01\i2c_pal_links.item
LinkGrp
false
false
true
Link0
false
false
clockMan1
Link1
false
false
intMan1
Link3
false
false
dmaController1
Link2
false
false
osif1
SdkSpecificMethods
1
i2c_palgroup
false
false
I2C_MasterInit
false
0
true
true
always
I2C_MasterInit
I2C_MasterSendData
false
0
true
true
always
I2C_MasterSendData
I2C_MasterSendDataBlocking
false
0
true
true
always
I2C_MasterSendDataBlocking
I2C_MasterReceiveData
false
0
true
true
always
I2C_MasterReceiveData
I2C_MasterReceiveDataBlocking
false
0
true
true
always
I2C_MasterReceiveDataBlocking
I2C_MasterSetSlaveAddress
false
0
true
true
always
I2C_MasterSetSlaveAddress
I2C_MasterGetTransferStatus
false
0
true
true
always
I2C_MasterGetTransferStatus
I2C_MasterSetBaudRate
false
0
true
true
always
I2C_MasterSetBaudRate
I2C_MasterGetBaudRate
false
0
true
true
always
I2C_MasterGetBaudRate
I2C_MasterAbortTransfer
false
0
true
true
always
I2C_MasterAbortTransfer
I2C_MasterDeinit
false
0
true
true
always
I2C_MasterDeinit
I2C_GetDefaultMasterConfig
false
0
true
true
always
I2C_GetDefaultMasterConfig
I2C_GetDefaultSlaveConfig
false
0
true
true
always
I2C_GetDefaultSlaveConfig
I2C_SlaveInit
false
0
true
true
always
I2C_SlaveInit
I2C_SlaveSendData
false
0
true
true
always
I2C_SlaveSendData
I2C_SlaveSendDataBlocking
false
0
true
true
always
I2C_SlaveSendDataBlocking
I2C_SlaveReceiveData
false
0
true
true
always
I2C_SlaveReceiveData
I2C_SlaveReceiveDataBlocking
false
0
true
true
always
I2C_SlaveReceiveDataBlocking
I2C_SlaveSetRxBuffer
false
0
true
true
always
I2C_SlaveSetRxBuffer
I2C_SlaveSetTxBuffer
false
0
true
true
always
I2C_SlaveSetTxBuffer
I2C_SlaveDeinit
false
0
true
true
always
I2C_SlaveDeinit
I2C_SlaveGetTransferStatus
false
0
true
true
always
I2C_SlaveGetTransferStatus
I2C_SlaveAbortTransfer
false
0
true
true
always
I2C_SlaveAbortTransfer
file:/${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0/tools/pex/Repositories/SDK_S32K1xx_15_Repository
com.freescale.processorexpert.ksdk.edma
edma
dmaController1
9
true
ALWAYS_WRITE
DMA_LDD
Referenced_Components
SDK_S32K1xx_15
false
DeviceName
false
false
dmaController1
PeriphDevice
false
false
DMA
false
CompVersion
S32_SDK_DMA_4CH
DummyProperty
false
false
0
VersionSpecificItem
1
Settings
false
false
PropertiesItem
1
Beans\edma\Items\S32_SDK_DMA_4CH\edma_properties.item
Configuration_group
false
false
0
true
InitStateStruct
false
false
dmaController1_State
ExternalObjectDeclaration
false
false
(string list)
edmaCfg
false
1
false
true
Beans\edma\Items\S32_SDK_DMA_4CH\edma_edmaCfg.item
edmaCfg_0
false
false
false
true
true
edmaCfg_NAME0
false
false
dmaController1_InitConfig0
edmaCfg_TYPE0
edma_user_config_t
edmaCfg_READONLY0
false
false
false
0
true
ChnArbitration0
false
false
false
0
EDMA_ARBITRATION_FIXED_PRIORITY
HaltOnError0
false
false
false
1
false
ChannelsInit
1
Beans\edma\Items\S32_SDK_DMA_4CH\edma_channelsInit.item
ChannelsInitItem
false
false
true
edmaChannelsConfig
false
1
false
true
Beans\edma\Items\S32_SDK_DMA_4CH\edma_channelCfg.item
edmaChannelCfg_0
false
true
true
ChnStateStruct0
false
false
dmaController1Chn0_State
ChnConfigStructName0
false
false
dmaController1Chn0_Config
ChnConfigStructType0
edma_channel_config_t
chnNumber0
false
false
false
type_edma_channel_number_s32k11x
0
0U
chnPriority0
false
false
false
0
EDMA_CHN_DEFAULT_PRIORITY
chnRequest0
false
false
false
type_edma_channel_request_s32k118
0
EDMA_REQ_DISABLED
CallbackName0
false
false
NULL
CallbackParam0
false
false
NULL
PeriodicTrigger0
false
false
false
1
false
LinkItem
1
Beans\edma\Items\S32_SDK_DMA_4CH\edma_links.item
LinkGrp
false
false
true
Link1
false
false
intMan1
Link2
false
false
clockMan1
SdkSpecificMethods
1
Beans\edma\Items\S32_SDK_DMA_4CH\edma_methods.item
edmagroup
false
false
EDMA_DRV_Init
false
0
true
true
always
EDMA_DRV_Init
EDMA_DRV_Deinit
false
0
true
true
always
EDMA_DRV_Deinit
EDMA_DRV_ChannelInit
false
0
true
true
always
EDMA_DRV_ChannelInit
EDMA_DRV_ReleaseChannel
false
0
true
true
always
EDMA_DRV_ReleaseChannel
EDMA_DRV_StartChannel
false
0
true
true
always
EDMA_DRV_StartChannel
EDMA_DRV_StopChannel
false
0
true
true
always
EDMA_DRV_StopChannel
EDMA_DRV_InstallCallback
false
0
true
true
always
EDMA_DRV_InstallCallback
EDMA_DRV_GetChannelStatus
false
0
true
true
always
EDMA_DRV_GetChannelStatus
EDMA_DRV_PushConfigToReg
false
0
true
true
always
EDMA_DRV_PushConfigToReg
EDMA_DRV_PushConfigToSTCD
false
0
true
true
always
EDMA_DRV_PushConfigToSTCD
EDMA_DRV_ConfigSingleBlockTransfer
false
0
true
true
always
EDMA_DRV_ConfigSingleBlockTransfer
EDMA_DRV_ConfigLoopTransfer
false
0
true
true
always
EDMA_DRV_ConfigLoopTransfer
EDMA_DRV_ConfigScatterGatherTransfer
false
0
true
true
always
EDMA_DRV_ConfigScatterGatherTransfer
EDMA_DRV_ConfigMultiBlockTransfer
false
0
true
true
always
EDMA_DRV_ConfigMultiBlockTransfer
EDMA_DRV_CancelTransfer
false
0
true
true
always
EDMA_DRV_CancelTransfer
EDMA_DRV_SetChannelRequestAndTrigger
false
0
true
true
always
EDMA_DRV_SetChannelRequestAndTrigger
EDMA_DRV_ClearTCD
false
0
true
true
always
EDMA_DRV_ClearTCD
EDMA_DRV_SetSrcAddr
false
0
true
true
always
EDMA_DRV_SetSrcAddr
EDMA_DRV_SetSrcOffset
false
0
true
true
always
EDMA_DRV_SetSrcOffset
EDMA_DRV_SetSrcReadChunkSize
false
0
true
true
always
EDMA_DRV_SetSrcReadChunkSize
EDMA_DRV_SetDestAddr
false
0
true
true
always
EDMA_DRV_SetDestAddr
EDMA_DRV_SetDestOffset
false
0
true
true
always
EDMA_DRV_SetDestOffset
EDMA_DRV_SetDestWriteChunkSize
false
0
true
true
always
EDMA_DRV_SetDestWriteChunkSize
EDMA_DRV_SetMinorLoopBlockSize
false
0
true
true
always
EDMA_DRV_SetMinorLoopBlockSize
EDMA_DRV_SetMajorLoopIterationCount
false
0
true
true
always
EDMA_DRV_SetMajorLoopIterationCount
EDMA_DRV_GetRemainingMajorIterationsCount
false
0
true
true
always
EDMA_DRV_GetRemainingMajorIterationsCount
EDMA_DRV_SetScatterGatherLink
false
0
true
true
always
EDMA_DRV_SetScatterGatherLink
EDMA_DRV_DisableRequestsOnTransferComplete
false
0
true
true
always
EDMA_DRV_DisableRequestsOnTransferComplete
EDMA_DRV_SetSrcLastAddrAdjustment
false
0
true
true
always
EDMA_DRV_SetSrcLastAddrAdjustment
EDMA_DRV_SetDestLastAddrAdjustment
false
0
true
true
always
EDMA_DRV_SetDestLastAddrAdjustment
EDMA_DRV_ConfigureInterrupt
false
0
true
true
always
EDMA_DRV_ConfigureInterrupt
EDMA_DRV_TriggerSwRequest
false
0
true
true
always
EDMA_DRV_TriggerSwRequest
file:/${ProcessorExpert_loc}/../../S32DS/software/S32SDK_S32K1xx_RTM_3.0.0/tools/pex/Repositories/SDK_S32K1xx_15_Repository
com.freescale.processorexpert.ksdk.lpuart
lpuart
lpuart1
11
true
ALWAYS_WRITE
PHONE_LDD
SDK_S32K1xx_15
false
DeviceName
false
false
lpuart1
PeriphDevice
false
false
LPUART1
false
CompVersion
S32K144_SDK01
VersionSpecificItem
1
Settings
false
false
PropertiesItem
1
Configuration_group
false
false
0
true
InitStateStruct
false
false
lpuart1_State
Configuration
false
1
false
true
Configuration_0
false
false
false
true
true
Configuration_NAME0
false
false
lpuart1_InitConfig0
Configuration_TYPE0
lpuart_user_config_t
Configuration_READONLY0
false
false
false
0
true
TransferType0
false
false
false
0
LPUART_USING_INTERRUPTS
BaudRate0
false
false
false
115200
DEC
clockIndex0
false
false
false
0
DEC
ActualBaudRate0
false
115942
DEC
Parity0
false
false
false
0
LPUART_PARITY_DISABLED
StopBits0
false
false
false
0
LPUART_ONE_STOP_BIT
DataBits0
false
false
false
0
LPUART_8_BITS_PER_CHAR
RxDMAChannel0
true
false
false
0
0U
TxDMAChannel0
true
false
false
DMAchannel_t
0
0U
LinkItem
1
Beans\lpuart\Items\S32K144_SDK01\lpuart_links.item
LinkGrp
false
false
true
Link1
false
false
clockMan1
Link2
false
false
dmaController1
Link3
false
false
osif1
SdkSpecificMethods
1
Beans\lpuart\Items\S32K144_SDK01\lpuart_methods.item
lpuart_irqgroup
false
false
LPUART_DRV_GetDefaultConfig
false
0
true
true
always
LPUART_DRV_GetDefaultConfig
LPUART_DRV_Init
false
0
true
true
always
LPUART_DRV_Init
LPUART_DRV_Deinit
false
0
true
true
always
LPUART_DRV_Deinit
LPUART_DRV_InstallRxCallback
false
0
true
true
always
LPUART_DRV_InstallRxCallback
LPUART_DRV_InstallTxCallback
false
0
true
true
always
LPUART_DRV_InstallTxCallback
LPUART_DRV_SendDataBlocking
false
0
true
true
always
LPUART_DRV_SendDataBlocking
LPUART_DRV_SendDataPolling
false
0
true
true
always
LPUART_DRV_SendDataPolling
LPUART_DRV_SendData
false
0
true
true
always
LPUART_DRV_SendData
LPUART_DRV_GetTransmitStatus
false
0
true
true
always
LPUART_DRV_GetTransmitStatus
LPUART_DRV_AbortSendingData
false
0
true
true
always
LPUART_DRV_AbortSendingData
LPUART_DRV_ReceiveDataBlocking
false
0
true
true
always
LPUART_DRV_ReceiveDataBlocking
LPUART_DRV_ReceiveDataPolling
false
0
true
true
always
LPUART_DRV_ReceiveDataPolling
LPUART_DRV_ReceiveData
false
0
true
true
always
LPUART_DRV_ReceiveData
LPUART_DRV_GetReceiveStatus
false
0
true
true
always
LPUART_DRV_GetReceiveStatus
LPUART_DRV_AbortReceivingData
false
0
true
true
always
LPUART_DRV_AbortReceivingData
LPUART_DRV_SetBaudRate
false
0
true
true
always
LPUART_DRV_SetBaudRate
LPUART_DRV_GetBaudRate
false
0
true
true
always
LPUART_DRV_GetBaudRate
LPUART_DRV_SetTxBuffer
false
0
true
true
always
LPUART_DRV_SetTxBuffer
LPUART_DRV_SetRxBuffer
false
0
true
true
always
LPUART_DRV_SetRxBuffer