282 lines
13 KiB
C
282 lines
13 KiB
C
/* ###################################################################
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** This component module is generated by Processor Expert. Do not modify it.
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** Filename : clockMan1.c
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** Project : S32K118_reva1_BaseDemo_LQFP48
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** Processor : S32K118_48
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** Component : clock_manager
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** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000
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** Repository : SDK_S32K1xx_15
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** Compiler : GNU C Compiler
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** Date/Time : 2021-09-16, 21:36, # CodeGen: 6
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**
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** Copyright 1997 - 2015 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** All Rights Reserved.
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**
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** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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** THE POSSIBILITY OF SUCH DAMAGE.
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** ###################################################################*/
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/*!
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** @file clockMan1.c
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** @version 01.00
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*/
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/*!
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** @addtogroup clockMan1_module clockMan1 module documentation
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** @{
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*/
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/* clockMan1. */
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#include "clockMan1.h"
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/**
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* @page misra_violations MISRA-C:2012 violations
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*
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* @section [global]
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* Violates MISRA 2012 Required Rule 9.4, Duplicate initialization of object element.
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* It's the only way to initialize an array that is member of struct.
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*
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* @section [global]
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* Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static.
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* The external variables will be used in other source files in application code.
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*/
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/* *************************************************************************
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* Configuration structure for peripheral clock configuration 0
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* ************************************************************************* */
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/*! @brief peripheral clock configuration 0 */
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peripheral_clock_config_t peripheralClockConfig0[NUM_OF_PERIPHERAL_CLOCKS_0] = {
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{
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.clockName = DMAMUX0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = FLEXIO0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPI2C0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPUART0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPUART1_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTA_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTB_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTC_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTD_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTE_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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};
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/* *************************************************************************
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* Configuration structure for Clock Configuration 0
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* ************************************************************************* */
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/*! @brief User Configuration structure clockMan1_InitConfig0 */
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clock_manager_user_config_t clockMan1_InitConfig0 = {
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/*! @brief Configuration of SIRC */
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.scgConfig =
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{
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.sircConfig =
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{
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.initialize = true, /*!< Initialize */
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/* SIRCCSR */
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.enableInStop = false, /*!< SIRCSTEN */
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.enableInLowPower = true, /*!< SIRCLPEN */
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.locked = false, /*!< LK */
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/* SIRCCFG */
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.range = SCG_SIRC_RANGE_HIGH, /*!< RANGE - High range (8 MHz) */
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/* SIRCDIV */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /*!< SIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /*!< SIRCDIV2 */
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},
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.fircConfig =
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{
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.initialize = true, /*!< Initialize */
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/* FIRCCSR */
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.regulator = true, /*!< FIRCREGOFF */
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.locked = false, /*!< LK */
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/* FIRCCFG */
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.range = SCG_FIRC_RANGE_48M, /*!< RANGE */
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/* FIRCDIV */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /*!< FIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /*!< FIRCDIV2 */
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},
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.rtcConfig =
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{
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.initialize = true, /*!< Initialize */
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.rtcClkInFreq = 0U, /*!< RTC_CLKIN */
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},
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.soscConfig =
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{
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.initialize = false, /*!< Do not initialize*/
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},
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.spllConfig =
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{
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.initialize = false, /*!< Do not initialize*/
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},
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.clockOutConfig =
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{
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.initialize = true, /*!< Initialize */
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.source = SCG_CLOCKOUT_SRC_FIRC, /*!< SCG CLKOUTSEL */
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},
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.clockModeConfig =
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{
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.initialize = true, /*!< Initialize */
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.rccrConfig = /*!< RCCR - Run Clock Control Register */
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{
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.src = SCG_SYSTEM_CLOCK_SRC_FIRC, /*!< SCS */
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.divCore = SCG_SYSTEM_CLOCK_DIV_BY_1, /*!< DIVCORE */
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.divBus = SCG_SYSTEM_CLOCK_DIV_BY_2, /*!< DIVBUS */
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.divSlow = SCG_SYSTEM_CLOCK_DIV_BY_2, /*!< DIVSLOW */
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},
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.vccrConfig = /*!< VCCR - VLPR Clock Control Register */
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /*!< SCS */
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.divCore = SCG_SYSTEM_CLOCK_DIV_BY_2, /*!< DIVCORE */
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.divBus = SCG_SYSTEM_CLOCK_DIV_BY_1, /*!< DIVBUS */
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.divSlow = SCG_SYSTEM_CLOCK_DIV_BY_4, /*!< DIVSLOW */
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},
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},
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},
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.pccConfig =
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{
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.peripheralClocks = peripheralClockConfig0, /*!< Peripheral clock control configurations */
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.count = NUM_OF_PERIPHERAL_CLOCKS_0, /*!< Number of the peripheral clock control configurations */
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},
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.simConfig =
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{
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.clockOutConfig = /*!< Clock Out configuration. */
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{
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.initialize = true, /*!< Initialize */
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.enable = false, /*!< CLKOUTEN */
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.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /*!< CLKOUTSEL */
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.divider = SIM_CLKOUT_DIV_BY_1, /*!< CLKOUTDIV */
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},
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.lpoClockConfig = /*!< Low Power Clock configuration. */
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{
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.initialize = true, /*!< Initialize */
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.enableLpo1k = true, /*!< LPO1KCLKEN */
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.enableLpo32k = true, /*!< LPO32KCLKEN */
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.sourceLpoClk = SIM_LPO_CLK_SEL_LPO_128K, /*!< LPOCLKSEL */
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.sourceRtcClk = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /*!< RTCCLKSEL */
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},
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.platGateConfig = /*!< Platform Gate Clock configuration. */
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{
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.initialize = true, /*!< Initialize */
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.enableMscm = true, /*!< CGCMSCM */
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.enableMpu = true, /*!< CGCMPU */
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.enableDma = true, /*!< CGCDMA */
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.enableErm = true, /*!< CGCERM */
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.enableEim = true, /*!< CGCEIM */
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},
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.qspiRefClkGating = /*!< Quad Spi Internal Reference Clock Gating. */
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{
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.enableQspiRefClk = false, /*!< Qspi reference clock gating */
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},
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.tclkConfig = /*!< TCLK CLOCK configuration. */
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{
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.initialize = true, /*!< Initialize */
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.tclkFreq[0] = 0U, /*!< TCLK0 */
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.tclkFreq[1] = 0U, /*!< TCLK1 */
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.tclkFreq[2] = 0U, /*!< TCLK2 */
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},
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.traceClockConfig = /*!< Debug trace Clock Configuration. */
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{
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.initialize = true, /*!< Initialize */
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.divEnable = true, /*!< TRACEDIVEN */
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.source = CLOCK_TRACE_SRC_CORE_CLK, /*!< TRACECLK_SEL */
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.divider = 0U, /*!< TRACEDIV */
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.divFraction = false, /*!< TRACEFRAC */
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},
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},
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.pmcConfig =
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{
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.lpoClockConfig = /*!< Low Power Clock configuration. */
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{
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.initialize = true, /*!< Initialize */
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.enable = true, /*!< Enable/disable LPO */
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.trimValue = 0, /*!< Trimming value for LPO */
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},
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},
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};
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/*! @brief Array of pointers to User configuration structures */
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clock_manager_user_config_t const * g_clockManConfigsArr[] = {
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&clockMan1_InitConfig0
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};
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/*! @brief Array of pointers to User defined Callbacks configuration structures */
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clock_manager_callback_user_config_t * g_clockManCallbacksArr[] = {(void*)0};
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/* END clockMan1. */
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/*!
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** @}
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*/
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/*
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** ###################################################################
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**
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** This file was created by Processor Expert 10.1 [05.21]
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** for the Freescale S32K series of microcontrollers.
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**
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** ###################################################################
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*/
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