396 lines
13 KiB
C
396 lines
13 KiB
C
/**
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* @page misra_violations MISRA-C:2012 violations
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*
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* @section [global]
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* Violates MISRA 2012 Required Rule 9.4, Duplicate initialization of object element.
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* It's the only way to initialize an array that is member of struct.
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*
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* @section [global]
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* Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static.
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* The external variables will be used in other source files in application code.
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*/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v13.0
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processor: S32K118
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package_id: S32K118_LQFP48
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mcu_data: s32sdk_s32k1xx_rtm_401
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processor_version: 0.0.0
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: ADC0_CLK.outFreq, value: 8 MHz}
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- {id: BUS_CLK.outFreq, value: 48 MHz}
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- {id: CLKOUT.outFreq, value: 48 MHz}
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- {id: CMP0_CLK.outFreq, value: 48 MHz}
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- {id: CORE_CLK.outFreq, value: 48 MHz}
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- {id: CRC0_CLK.outFreq, value: 48 MHz}
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- {id: DMA0_CLK.outFreq, value: 48 MHz}
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- {id: DMAMUX0_CLK.outFreq, value: 48 MHz}
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- {id: EIM0_CLK.outFreq, value: 48 MHz}
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- {id: ERM0_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
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- {id: FLASH_CLK.outFreq, value: 24 MHz}
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- {id: FLEXCAN0_CLK.outFreq, value: 48 MHz}
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- {id: FTFC0_CLK.outFreq, value: 24 MHz}
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- {id: FTM0_CLK.outFreq, value: 8 MHz}
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- {id: FTM1_CLK.outFreq, value: 8 MHz}
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- {id: FlexIO0_CLK.outFreq, value: 8 MHz}
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- {id: LPI2C0_CLK.outFreq, value: 8 MHz}
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- {id: LPIT0_CLK.outFreq, value: 8 MHz}
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- {id: LPO_1K_CLK.outFreq, value: 1 kHz}
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- {id: LPO_CLK.outFreq, value: 128 kHz}
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- {id: LPSPI0_CLK.outFreq, value: 8 MHz}
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- {id: LPSPI1_CLK.outFreq, value: 8 MHz}
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- {id: LPTMR0_CLK.outFreq, value: 8 MHz}
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- {id: LPUART0_CLK.outFreq, value: 8 MHz}
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- {id: LPUART1_CLK.outFreq, value: 8 MHz}
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- {id: MPU0_CLK.outFreq, value: 48 MHz}
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- {id: MSCM0_CLK.outFreq, value: 48 MHz}
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- {id: PDB0_CLK.outFreq, value: 48 MHz}
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- {id: PORTA_CLK.outFreq, value: 48 MHz}
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- {id: PORTB_CLK.outFreq, value: 48 MHz}
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- {id: PORTC_CLK.outFreq, value: 48 MHz}
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- {id: PORTD_CLK.outFreq, value: 48 MHz}
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- {id: PORTE_CLK.outFreq, value: 48 MHz}
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- {id: RTC0_CLK.outFreq, value: 48 MHz}
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- {id: RTC_CLK.outFreq, value: 48 MHz}
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- {id: SCGCLKOUT.outFreq, value: 48 MHz}
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- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
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- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
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- {id: SYS_CLK.outFreq, value: 48 MHz}
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- {id: TRACE_CLK.outFreq, value: 48 MHz}
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settings:
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- {id: CLKOUTDIV.scale, value: '1', locked: true}
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- {id: PCC.LPTMR0_FRAC.scale, value: '1', locked: true}
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- {id: PCC.PREDIV.scale, value: '1', locked: true}
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- {id: PCC.PREDIVTRACE.scale, value: '1', locked: true}
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- {id: PCC.TRACE_FRAC.scale, value: '1', locked: true}
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- {id: RTCCLKSEL.sel, value: SCG.FIRCDIV1_CLK}
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- {id: 'RUN:SCG.DIVBUS.scale', value: '1', locked: true}
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- {id: 'RUN:SCG.DIVCORE.scale', value: '1', locked: true}
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- {id: 'RUN:SCG.DIVSLOW.scale', value: '2', locked: true}
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- {id: SCG.DIVBUS.scale, value: '1', locked: true}
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- {id: SCG.DIVCORE.scale, value: '1', locked: true}
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- {id: SCG.DIVSLOW.scale, value: '2', locked: true}
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- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
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- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
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- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
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- {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
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- {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
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- {id: SCG.SOSCDIV2.scale, value: '1', locked: true}
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- {id: 'VLPR:SCG.DIVBUS.scale', value: '1', locked: true}
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- {id: 'VLPR:SCG.DIVCORE.scale', value: '2', locked: true}
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- {id: 'VLPR:SCG.DIVSLOW.scale', value: '4', locked: true}
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- {id: 'VLPR:SCG.SCSSEL.sel', value: SCG.SIRC}
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sources:
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- {id: SCG.SOSC.outFreq, value: 8 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* *************************************************************************
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* Configuration structure for peripheral clock configuration 0
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* ************************************************************************* */
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/*! @brief peripheral clock configuration 0 */
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peripheral_clock_config_t peripheralClockConfig0[NUM_OF_PERIPHERAL_CLOCKS_0] = {
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{
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.clockName = ADC0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPSPI0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPSPI1_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPUART0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPUART1_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPI2C0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPIT0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = LPTMR0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = FTM0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV1,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = FTM1_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV1,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = FLEXIO0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_SIRC_DIV2,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = CMP0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = CRC0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = DMAMUX0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = FTFC0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PDB0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = RTC0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = FlexCAN0_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTA_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTB_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTC_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTD_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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{
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.clockName = PORTE_CLK,
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.clkGate = true,
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.clkSrc = CLK_SRC_OFF,
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.frac = MULTIPLY_BY_ONE,
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.divider = DIVIDE_BY_ONE,
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},
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};
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/* *************************************************************************
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* Configuration structure for Clock Configuration 0
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* ************************************************************************* */
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/*! @brief User Configuration structure clock_managerCfg_0 */
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clock_manager_user_config_t clockMan1_InitConfig0 = {
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.scgConfig =
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{
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.sircConfig =
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{
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.initialize = true,
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.enableInStop = true, /* Enable SIRC in stop mode */
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.enableInLowPower = true, /* Enable SIRC in low power mode */
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.locked = false, /* unlocked */
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.range = SCG_SIRC_RANGE_HIGH, /* Slow IRC high range clock (8 MHz) */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* Slow IRC Clock Divider 1: divided by 1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* Slow IRC Clock Divider 3: divided by 1 */
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},
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.fircConfig =
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{
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.initialize = true,
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.regulator = true, /* FIRC regulator is enabled */
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.locked = false, /* unlocked */
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.range = SCG_FIRC_RANGE_48M, /*!< RANGE */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* Fast IRC Clock Divider 1: divided by 1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* Fast IRC Clock Divider 3: divided by 1 */
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},
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.rtcConfig =
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{
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.initialize = false,
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},
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.soscConfig =
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{
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.initialize = false,
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},
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.clockOutConfig =
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{
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.initialize = true,
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.source = SCG_CLOCKOUT_SRC_FIRC, /* Fast IRC. */
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},
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.clockModeConfig =
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{
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.initialize = true,
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.rccrConfig =
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{
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.src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* Fast IRC */
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.divCore = SCG_SYSTEM_CLOCK_DIV_BY_1,/* Core Clock Divider: divided by 1 */
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.divBus = SCG_SYSTEM_CLOCK_DIV_BY_1,/* Bus Clock Divider: divided by 1 */
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.divSlow = SCG_SYSTEM_CLOCK_DIV_BY_2,/* Slow Clock Divider: divided by 2 */
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},
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.vccrConfig =
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* Slow IRC */
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.divCore = SCG_SYSTEM_CLOCK_DIV_BY_2,/* Core Clock Divider: divided by 2 */
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.divBus = SCG_SYSTEM_CLOCK_DIV_BY_1,/* Bus Clock Divider: divided by 1 */
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.divSlow = SCG_SYSTEM_CLOCK_DIV_BY_4,/* Slow Clock Divider: divided by 4 */
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},
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},
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},
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.pccConfig =
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{
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.peripheralClocks = peripheralClockConfig0, /*!< Peripheral clock control configurations */
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.count = NUM_OF_PERIPHERAL_CLOCKS_0, /*!< Number of the peripheral clock control configurations */
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},
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.simConfig =
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{
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.clockOutConfig =
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{
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.initialize = true, /*!< Initialize */
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.enable = true, /* enabled */
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.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT,/* SCG CLKOUT clock select: SCG slow clock */
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.divider = SIM_CLKOUT_DIV_BY_1, /* Divided by 1 */
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},
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.lpoClockConfig =
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{
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.initialize = true, /*!< Initialize */
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.enableLpo1k = true, /*!< LPO1KCLKEN */
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.enableLpo32k = true, /*!< LPO32KCLKEN */
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.sourceLpoClk = SIM_LPO_CLK_SEL_LPO_128K,/* 128 kHz LPO clock */
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.sourceRtcClk = SIM_RTCCLK_SEL_FIRCDIV1_CLK,/* FIRCDIV1 clock */
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},
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.platGateConfig =
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{
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.initialize = true, /*!< Initialize */
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.enableEim = true, /*!< CGCEIM */
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.enableErm = true, /*!< CGCERM */
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.enableDma = true, /*!< CGCDMA */
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.enableMpu = true, /*!< CGCMPU */
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.enableMscm = true, /*!< CGCMSCM */
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},
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.tclkConfig =
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{
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.initialize = false, /*!< Initialize */
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},
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.traceClockConfig =
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{
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.initialize = true, /*!< Initialize */
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.divEnable = true, /*!< TRACEDIVEN */
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.source = CLOCK_TRACE_SRC_CORE_CLK, /*!< TRACECLK_SEL */
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.divider = 0U, /*!< TRACEDIV */
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.divFraction = false, /*!< TRACEFRAC */
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},
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},
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.pmcConfig =
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{
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.lpoClockConfig =
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{
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.initialize = true, /*!< Initialize */
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.enable = true, /*!< Enable/disable LPO */
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.trimValue = 0, /*!< Trimming value for LPO */
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},
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},
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};
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/*! @brief Array of pointers to User configuration structures */
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clock_manager_user_config_t const * g_clockManConfigsArr[] = {
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&clockMan1_InitConfig0
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};
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/*! @brief Array of pointers to User defined Callbacks configuration structures */
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/* The tool do not support generate Callbacks configuration. It's always empty. */
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clock_manager_callback_user_config_t * g_clockManCallbacksArr[] = {(void*)0};
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